A class of turbo-like codes with efficient and practical high-speed decoders

Proceedings - IEEE Military Communications Conference MILCOM

Volumn 1, Issue , 2004, Pages 245-250

  Abbasfar, Aliazam ^a   Divsalar, Dariush ^b   KungYao, ^a  

^a University of California   (United States)

^b CALIFORNIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DECODERS; HIGH-SPEED DECODING; LOW DENSITY PARITY CHECK (LDPC) CODES; SHANNON-CAPACITY PERFORMANCE;

COMPUTER ARCHITECTURE; DECODING; PARALLEL PROCESSING SYSTEMS; VLSI CIRCUITS;

TURBO CODES;

EID: 27744589192     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)

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2. S. Benedetto, D. Divsalar, G. Montorsi, and F. Pollara, "Soft-input Soft-output APP module for iterative decoding of concatenated codes," IEEE Commu. Letters vol. 1, pp.22-24, Jan. 97.
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9. Jeremy Thorpe, " Low Density Parity Check (LDPC) Codes Constructed from Protographs," JPL INP Progress Report 42-154, August 15, 2003.
10. Richardson , et al., " Methods and apparatus for decoding LDPC codes," United States Patent 6,633,856, October 14, 2003.
11. A. Abbasfar, D. Divsalar, and K. Yao,"Accumulate Repeat Accumulate Codes," IEEE ISIT 2004, Chicago, IL, June 27-July 2, 2004.