Memory module selection for high level synthesis

IEEE Workshop on VLSI Signal Processing, Proceedings

Volumn , Issue , 1996, Pages 273-282

  Sentieys, O ^a   Chillet, D ^a   Diguet, J P ^a   Philippe, J L ^a  

^a UNIVERSITÉ DE RENNES 1   (France)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; DESIGN; MICROPROCESSOR CHIPS; TELECOMMUNICATION SYSTEMS; VLSI CIRCUITS;

HIGH LEVEL SYNTHESIS; MEMORY MODULE SELECTION;

DATA STORAGE EQUIPMENT;

EID: 0030400486     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (16)