Exact memory size estimation for array computations

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 8, Issue 5, 2000, Pages 517-521

  Zhao, Ying ^a   Malik, Sharad ^a  

^a Princeton University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CALCULATIONS; COMPUTATIONAL COMPLEXITY; DIGITAL SIGNAL PROCESSING; ESTIMATION; ITERATIVE METHODS; MATHEMATICAL MODELS;

ARRAY COMPUTATIONS; INTEGER POINT COUNTING; LIVE VARIABLE ANALYSIS; MEMORY SIZE; POLYTOPE MODELS;

ALGORITHMS;

EID: 0034289947     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.894155     Document Type: Article

References (9)

1. F. Balasa, F. Catthoor, and H. D. Man, "Background memory area estimation for multi-dimensional signal processing systems," IEEE Trans. VLSI Syst., vol. 3, pp. 157-172, June 1995.
2. P. Clauss, "Counting solutions to linear and nonlinear constraints through ehrhart polynomials: Applications to analyze and transform scientific programs," in Proc. 10th ACM Int. Conf. Supercomputing (ICS'96), May 1996.
3. _, "Handling memory cache policy with integer points countings," in Proc. Euro-Par'97, Aug. 1997, pp. 285-293.
4. F. Kurdahi and A. Parker, "Real: A program for register allocation," in Proc. 24th Design Automation Conf., June 1987, pp. 210-215.
5. G. Chaitin, M. Auslander, A. Chandra, J. Cocke, M. Hopkins, and P. Markstein, "Register allocation and spilling via graph coloring," Comput. Lang., vol. 6, 1981.
6. P. Grun, F. Balasa, and N. Dutt, "Memory size estimation for multimedia applications," in Proc. Workshop Hardware/Software Codesign(CODES/CACHE), March 1998.
7. C. Lengauer, "Loop parallelization in the polytope model," in CONCUR'93, ser. Lecture Notes in Computer Science 715. Berlin, Germany: Springer-Verlag, 1993, pp. 398-416.
8. A. Sudarsanam and S. Malik, "Simultaneous reference allocation in code generation for dual data memory bank asips," ACM Trans. Design Automat. Electron. Syst., 1999, to be published.
9. C. Tseng and D. Siewiorek, "Automated synthesis of data paths in digital systems," IEEE Trans. Computer-Aided Design, vol. CAD-5, July 1986.