High-speed CRC computation using state-space transformations

Conference Record / IEEE Global Telecommunications Conference

Volumn 1, Issue , 2001, Pages 166-170

  Derby, Jeff H ^a  

^a IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL METHODS; ENCODING (SYMBOLS); FEEDBACK; GATES (TRANSISTOR); MATHEMATICAL TRANSFORMATIONS; PIPELINE PROCESSING SYSTEMS; POLYNOMIALS; REDUNDANCY; STATE SPACE METHODS; THROUGHPUT;

CYCLIC REDUNDANCY CHECK (CRC) COMPUTATIONS; FEEDBACK LOOPS;

SHIFT REGISTERS;

EID: 0035684646     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (13)

1. Cyclic codes for error detection
2. Serial-to-parallel transformation of linear-feedback shift-register circuits
3. A multi-channel CRC register
4. Byte-wise CRC calculations
5. Parallel CRC generation
6. High-speed parallel CRC circuits in VLSI
7. Parallel realization of the ATM cell header CRC
8. A two-step computation of cyclic redundancy code CRC-32 for ATM networks
9. Parallel encoders for cyclic codes using state-space transformations