High-speed architectures for parallel long BCH encoders

Proceedings of the ACM Great Lakes Symposium on VLSI

Volumn , Issue , 2004, Pages 1-6

  Zhang, Xinmiao ^a   Parhi, Keshab K ^a  

^a UNIVERSITY OF MINNESOTA   (United States)

Author keywords

BCH; Critical loop; Encoder; Fanout; Generator polynomial; Iteration bound; Linear feedback shift register; Parallel processing; Retiming; Un folding

Indexed keywords

ALGORITHMS; DATA COMMUNICATION SYSTEMS; FEEDBACK; ITERATIVE METHODS; OPTICAL COMMUNICATION; PARALLEL PROCESSING SYSTEMS; SHIFT REGISTERS; TELECOMMUNICATION SYSTEMS;

BCH; CRITICAL LOOP; GENERATOR POLYNOMIALS; LINEAR FEEDBACK SHIFT REGISTERS; RETIMING;

ERROR CORRECTION;

EID: 2942641862     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/988952.988954     Document Type: Conference Paper

References (6)

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