MOSFET matching improvement in 65nm technology providing gain on both analog and SRAM performances

IEEE International Conference on Microelectronic Test Structures

Volumn , Issue , 2005, Pages 137-142

  Difrenza, R ^a   Rochereau, K ^b   Devoivre, T ^a   Tavel, B ^b   Duriez, B ^b   Roy, D ^a   Jullian, S ^b   Dezzani, A ^a   Boulestin, R ^a   Stolk, P ^b   Arnaud, F ^a  

^a STMICROELECTRONICS   (France)

^b NXP SEMICONDUCTORS   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

LINEAR SYSTEMS; MICROELECTRONICS; STATIC RANDOM ACCESS STORAGE;

NMOS; PMOS; THERMAL BUDGETS;

MOSFET DEVICES;

EID: 27644508150     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

1. K. Lakshmikumar et al., Characterization and modeling of mismatch in MOS transistors for precision analog design, IEEE Journal of Solid State Circuits, vol. 21, p. 1057, 1986.
2. M. Pelgrom et al., Matching properties of MOS transistors, IEEE Journal of Solid State Circuits, vol. 24, p. 1433, 1989.
3. J. Croon et al., A comparison of extraction techniques for threshold voltage mismatch, ICMTS Proceedings, p.235, 2002.
4. H. Tuinhout et al., Effects of gate depletion and boron penetration on matching of deep submicron CMOS transistors, IEDM Proceedings., p. 631, 1997.
5. A. Asenov et al., Polysilicon gate of the random dopant induced threshold voltage fluctuations in sub-100nm MOSFET's with ultra thin oxide, IEEE Transactions on Electron Devices, p. 805, 2000.
6. R. Difrenza et al., Impact of grain number fluctuations in the MOS transistor gate on matching performance, ICMTS Proceedings, p.244, 2003.
7. M. Pelgrom et al., Matching properties of MOS transistors, IEEE Journal of Solid State Circuits, vol.34, p. 1433, 1989.