DVS for buffer-constrained architectures with predictable QoS-energy tradeoffs

CODES+ISSS 2005 - International Conference on Hardware/Software Codesign and System Synthesis

Volumn , Issue , 2005, Pages 111-116

  Maxiaguine, Alexander ^a   Chakraborty, Samarjit ^b   Thiele, Lothar ^a  

^a ETH ZURICH   (Switzerland)

^b NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

Author keywords

Buffer management; DVS; Predictable design; QoS

Indexed keywords

COMPUTER ARCHITECTURE; CONSTRAINT THEORY; ENERGY UTILIZATION; FEEDBACK; MULTIMEDIA SYSTEMS; QUALITY OF SERVICE;

BUFFER MANAGEMENT; DYNAMIC VOLTAGE AND FREQUENCY SCALING (DVS); MULTIMEDIA PROCESSING; PREDICTABLE DESIGN;

BUFFER STORAGE;

EID: 27644473259     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1084834.1084865     Document Type: Conference Paper

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