Dynamic Voltage Scheduling with Buffers in Low-Power Multimedia Applications

ACM Transactions on Embedded Computing Systems

Volumn 3, Issue 4, 2004, Pages 686-705

  Im, Chaeseok ^a   Ha, Soonhoi ^a   Kim, Huiseok ^a  

^a Seoul National University   (South Korea)

Author keywords

Algorithms; Buffer requirement estimation; dynamic voltage scheduling; low power systems; multimedia applications; Performance

Indexed keywords

EID: 84994656775     PISSN: 15399087     EISSN: 15583465     Source Type: Journal    
DOI: 10.1145/1027794.1027796     Document Type: Article

References (26)

1. Aydin, H., Melhem, R., Mosse, D., Mejia-Alvarez, P., 2001. Dynamic and aggressive scheduling techniques for power-aware real-time systems. In Proceedings of the 22nd IEEE Real-Time Systems Symposium.
2. Burd, T. D., Pering, T. A., Stratakos, A. J., Brodersen, R. W., 2000. A dynamic voltage scaled microprocessor system. IEEE J. Solid-State Circ. 35, 11 (Nov.), 1571-1580.
3. Catthoor, F., Wuytack, S., De Greef, E., Balasa, F., Nachtergaele, L., and Vandecappelle, A. 1998. Custom Memory Management Methodology. Kluwer Academic Publishers, Boston, MA, 73-77.
4. Chandrakasan, A. P., Sheng, S., Brodersen, R. W., 1992. Low-power CMOS digital design. IEEE J. Solid-State Circ. 27, 4 (Apr.), 473-484.
5. Chandrasena, L. H., Chandrasena, P., Liebelt, M. J., 2001. An energy efficient rate selection algorithm for voltage quantized dynamic voltage scaling. In Proceedings of 14th International Symposium on Systems and Synthesis.
6. Chandrasena, L. H., Liebelt, M. J., 2000. A rate selection algorithm for quantized undithered dynamic supply voltage scaling. In Proceedings of the International Symposium on Low Power and Electronics Design. 213-215.
7. Govil, K., Chan, E., Wasserman, H., 1995. Comparing algorithms for dynamic speed-setting of a low-power CPU. In Proceedings of the First Annual International Conference on Mobile Computing and Networking. 13-25.
8. Gutnik, V., 1996. Variable Supply Voltage for Low Power DSP. Masters Thesis, Massachusetts Institute of Technology.
9. Hong, I., Kirovski, D., Qu, G., Potkonjak, M., Srivastava, M. B., 1998. Power optimization of variable voltage core-based systems. In Proceedings of the 35th Design Automation Conference. 176-181.
10. Ishihara, T., Yasuura, H., 1998. Voltage scheduling problem for dynamically variable voltage processors. In Proceedings of the International Symposium on Low Power and Electronics Design. 197-202.
11. Jha, N. K., 2001. Low power system scheduling and synthesis. In Proceedings of the International Conference on Computer-Aided Design. 259-263.
12. Krishna, C. M., Lee, Y., 2000. Voltage-clock-scaling adaptive scheduling techniques for low power in hard real-time systems. In Proceedings of the 6th IEEE Real-Time Technology and Applications Symposium.
13. Lee, S., Sakurai, T., 2000. Run-time voltage hopping for low-power real-time systems. In Proceedings of the 37th Design Automation Conference. 806-809.
14. Mosse, D., Aydin, B., Childers, B., Melhem, R., 2000. Compiler-assisted dynamic power-aware scheduling for real-time applications. In Proceedings of a Workshop on Compilers and Operating Systems for Low Power.
15. Nielsen, L. S., Niessen, C., Sparso, J., Vanberkel, K., 1994. Low-power operation using self-timed circuits and adaptive scaling of the supply voltage. IEEE Trans. VLSI Syst. 2, 4 (Dec.), 391-397.
16. Okuma, T., Ishihara, T., Yasuura, H., 1999. Real-time task scheduling for a variable voltage processor. In Proceedings of the 12th International Symposium on Systems and Synthesis. 24-29.
17. Pering, T., Burd, T., Brodersen, R., 1998. The simulation and evaluation of dynamic voltage scaling algorithms. In Proceedings of the International Symposium on Low Power and Electronics Design. 76-81.
18. Pillai, P., Shin, K. G., 2001. Real-time dynamic voltage scaling for low-power embedded operating systems. In Proceedings of the ACM Symposium on Operating Systems Principles. 89-102.
19. Quan, G., Hu, X., 2001. Energy efficient fixed-priority scheduling for real-time systems on variable voltage processors. In Proceedings of the 38th Design Automation Conference. 828-833.
20. Shin, D., Kim, J., 2001. A profile-based energy-efficient intra-task voltage scheduling algorithm for hard real-time applications. In Proceedings of the International Symposium on Low Power and Electronics Design. 271-274.
21. Shin, D., Kim, J., Lee, S., 2001. Intratask voltage scheduling for low-energy hard real-time applications. IEEE Des. Test Comput. 18, 2 (Mar.-Apr.).
22. Shin, Y., Choi, K., 1999. Power conscious fixed priority scheduling for hard real-time systems. In Proceedings of the 36th Design Automation Conference. 134-139.
23. Shin, Y., Choi, K., Sakurai, T., 2000. Power optimization of real-time embedded systems on variable speed processors. In Proceedings of the International Conference on Computer-Aided Design. 365-368.
24. Weiser, M., Welch, B., Demers, A., Shenker, S., 1994. Scheduling for reduced CPU energy. In Proceedings of the First USENIX Symposium on Operating System Design and Implementation. 12-23.
25. Yao, F., Demers, A., Shenker, S., 1995. A scheduling model for reduced CPU energy. In Proceedings of the 36th IEEE Annual Symposium on Foundations of Computer Science. 374-381.
26. Zhu, D., Melhem, R., Childers, B., 2001. Scheduling with dynamic voltage/speed adjustment using slack reclamation in multi-processor real-time systems. In Proceedings of the 22nd IEEE Real-Time Systems Symposium. 84-94.