High-level synthesis for large bit-width multipliers on FPGAs: A case study

CODES+ISSS 2005 - International Conference on Hardware/Software Codesign and System Synthesis

Volumn , Issue , 2005, Pages 213-218

  Quan, Gang ^a   Davis, James P ^a   Devarkal, Siddhaveerasharan ^a   Buell, Duncan A ^a  

^a The Department of Mechanical Engineering   (United States)

Author keywords

Design Exploration; FPGA Devices; High Level Synthesis; Large scale Integer Multipliers; Reconfigurable Computing

Indexed keywords

CRYPTOGRAPHY; ERROR CORRECTION; FREQUENCY MULTIPLYING CIRCUITS; INTEGRATED CIRCUITS; MATHEMATICAL MODELS; MULTIMEDIA SYSTEMS;

DESIGN EXPLORATION; FPGA DEVICES; HIGH LEVEL SYNTHESIS; LARGE-SCALE INTEGER MULTIPLIERS; RECONFIGURABLE COMPUTING;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 27644456617     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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