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Volumn 3149, Issue , 2004, Pages 516-524

Contents management in first-level multibanked data caches

Author keywords

[No Author keywords available]

Indexed keywords

ECONOMIC AND SOCIAL EFFECTS; INTEGRATED CIRCUIT DESIGN;

EID: 27544492841     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-540-27866-5_68     Document Type: Article
Times cited : (2)

References (13)
  • 1
    • 0033717865 scopus 로고    scopus 로고
    • Clock Rate versus IPC: The End of the Road for Conventional Microarchitectures
    • V. Agarwal et al.: Clock Rate versus IPC: The End of the Road for Conventional Microarchitectures. Proc. of 27th ISCA (2000) 248-259.
    • (2000) Proc. of 27th ISCA , pp. 248-259
    • Agarwal, V.1
  • 4
    • 0035390811 scopus 로고    scopus 로고
    • A High-Bandwidth Memory Pipeline for Wide Issue Processors
    • S. Cho, P. Yew, and G. Lee: A High-Bandwidth Memory Pipeline for Wide Issue Processors. IEEE Trans, on Computers, vol. 50, no. 7 (2001) 709-723.
    • (2001) IEEE Trans, on Computers , vol.50 , Issue.7 , pp. 709-723
    • Cho, S.1    Yew, P.2    Lee, G.3
  • 6
    • 0030645118 scopus 로고    scopus 로고
    • Trading Conflict and Capacity Aliasing in Conditional Branch Predictors
    • P. Michaud, A. Seznec, and R. Uhlig: Trading Conflict and Capacity Aliasing in Conditional Branch Predictors. Proc. of 24th ISCA (1997) 292-303.
    • (1997) Proc. of 24th ISCA , pp. 292-303
    • Michaud, P.1    Seznec, A.2    Uhlig, R.3
  • 7
    • 0036858569 scopus 로고    scopus 로고
    • The implementation of the Itanium 2 Microprocessor
    • S. Naffziger et al.: The implementation of the Itanium 2 Microprocessor. IEEE J. Solid State Circuits, vol. 37, no. 11 (2002) 1448-1460.
    • (2002) IEEE J. Solid State Circuits , vol.37 , Issue.11 , pp. 1448-1460
    • Naffziger, S.1
  • 8
    • 0034581199 scopus 로고    scopus 로고
    • A Technique for High Bandwidth and- Deterministic Low Latency Load/Store Accesses to Multiple Cache Banks
    • H. Neefs, H. Vandierendonck, and K. De Bosschere: A Technique for High Bandwidth and- Deterministic Low Latency Load/Store Accesses to Multiple Cache Banks. Proc. of 6th HPCA (2000) 313-324.
    • (2000) Proc. of 6th HPCA , pp. 313-324
    • Neefs, H.1    Vandierendonck, H.2    De Bosschere, K.3
  • 9
    • 1142280992 scopus 로고    scopus 로고
    • Partitioned First-Level Cache Design for Clustered Microarchitectures
    • June
    • C. Racunas and Y.N. Patt: Partitioned First-Level Cache Design for Clustered Microarchitectures. Proc. of 17th ICS 22-31. June 2003.
    • (2003) Proc. of 17th ICS 22-31
    • Racunas, C.1    Patt, Y.N.2
  • 11
    • 0026141669 scopus 로고
    • High-Bandwidth Memory Systems for Superscalar Processors
    • G.S.-Sohi and M. Franklin: High-Bandwidth Memory Systems for Superscalar Processors. Proc. 4th ASPLOS (1991) 53-62.
    • (1991) Proc. 4th ASPLOS , pp. 53-62
    • Sohi, G.S.1    Franklin, M.2
  • 12
    • 35048824910 scopus 로고    scopus 로고
    • Counteracting Bank Mispredictions in Sliced First-Level Caches
    • 9th EuroPar, Sept.
    • E. Torres, P.E. Ibañez, V. Viñals, and J.M. Llabería: Counteracting Bank Mispredictions in Sliced First-Level Caches. 9th EuroPar, LNCS 2790 586-596, Sept. 2003.
    • (2003) LNCS , vol.2790 , pp. 586-596
    • Torres, E.1    Ibañez, P.E.2    Viñals, V.3    Llabería, J.M.4
  • 13
    • 0032651228 scopus 로고    scopus 로고
    • Speculation Techniques for Improving Load Related Instruction Scheduling
    • A. Yoaz, E. Mattan, R. Ronen, and S. Jourdan.: Speculation Techniques for Improving Load Related Instruction Scheduling. Proc. of 26th ISCA (1999) 42-53.
    • (1999) Proc. of 26th ISCA , pp. 42-53
    • Yoaz, A.1    Mattan, E.2    Ronen, R.3    Jourdan, S.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.