Improved interface quality and charge-trapping characteristics of MOSFETs with high-κ gate dielectric

IEEE Electron Device Letters

Volumn 26, Issue 10, 2005, Pages 725-727

  Park, Hokyung ^a   Rahman, M Shahriar ^a   Chang, Man ^a   Lee, Byoung Hun ^b   Choi, Rino ^b   Young, Chadwin D ^b   Hwang, Hyunsang ^a  

^a Gwangju Institute of Science and Technology (GIST)   (South Korea)

^b IBM   (United States)

Author keywords

Charge trapping; High pressure annealing; Interface trap density; Transconductance

Indexed keywords

DIELECTRIC MATERIALS; ELECTRIC CURRENTS; GATES (TRANSISTOR); HAFNIUM COMPOUNDS; HIGH PRESSURE EFFECTS; INTERFACES (MATERIALS); RAPID THERMAL ANNEALING; TRANSCONDUCTANCE;

CHARGE TRAPPING; HIGH PRESSURE ANNEALING; INTERFACE TRAP DENSITY;

MOSFET DEVICES;

EID: 27144536907     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2005.855422     Document Type: Article

References (12)

1. B. Guillaumot, X. Garros, F. Lime, K. Oshima, B. Tavel, J. A. Chroboczek, P. Masson, R. Truche, A. M. Papon, F. Martin, J. F. Damlencourt, S. Maitrejean, M. Rivoire, C. Leroux, S. Cristoloveanu, G. Ghibaudo, J. L. Autran, T. Skotnicki, and S. Deleonibus, "75 nm damascene metal gate and high-κ integration for advanced CMOS devices," in IEDM Tech. Dig., 2002, pp. 355-358.
2. J.-P. Han, E. M. Vogel, E. P. Gusev, C. D. Emic, C. A. Ritcher, D. W. Heh, and J. S. Suehle, "Energy distribution of interface traps in high-κ gated MOSFETs," in Symp. VLSI Tech. Dig., 2003, pp. 161-162.
3. 2 MOSFETs," IEDM Tech. Dig., pp. 659-662, 2001.
4. 2-based/polycrystalline-Si gate stacks," Appl. Phys. Lett., vol. 83, no. 3, pp. 533-535, 2003.
5. J. Lee, K. Cheng, Z. Chen, K. Hess, J. W. Lyding, Y. Kim, H. Lee, Y. Kim, and K. Suh, "Application of high pressure deuterium annealing for improving the hot cartier reliability of CMOS transistors," IEEE Electron Device Lett., vol. 21, no. 5, pp. 221-223, May 2000.
6. 2 gate stack," in Proc. IEEE Semicon. Interface Specialist Conf., 2003.
7. G. Bersuker, J. Gutt, N. Chaudhary, N. Moumen, B. H. Lee, J. Barnett, S. Gopalan, G. Brown, Y. Kim, C. D. Young, J. Peterson, H.-J. Li, P. M. Zeizoff, J. H. Sim, P. Lysaght, M. Gardner, R. W. Murto, and H. R. Huff, "Integration issues of high-κ gate stack: Process-induced charging," in Int. Reliab. Phys. Symp., 2004, pp. 479-484.
8. G. Groeseneken, H. E. Maes, N. Beltran, and R. F. De Keersmaecker, "A reliable approach to charge pumping measurements in MOS transistors," IEEE Trans. Electron Devices, vol. ED-31, no. 1, pp. 42-53, Jan. 1984.
9. P. Mason, J. L. Autran, and J. Brini, "On the tunneling component of charge pumping current in ultrathin gate oxide MOSFETs," IEEE Electron Device Lett., vol. 20, no. 2, pp. 92-94, Feb. 1999.
10. A. Kerber, E. Cartier, L. Pantisano, R. Degraeve, T. Kauerauf, Y. Kim, A. Hou, G. Groeseneken, H. E. Maes, and U. Schwalke, "Origin of the threshold voltage instability in SiO2/HfO2 dual layer gate dielectrics," IEEE Electron Device Lett., vol. 24, no. 2, pp. 87-89, Feb. 2003.
11. C. D. Young, G. Bersuker, G. A. Brown, P. Lysaght, P. Zeitzoff, R. W. Murto, and H. R. Huff, "Charge trapping and device performance degradation in MOCVD hafnium-based gate dielectric stack structures," in Proc. Int. Relia. Phys. Symp., 2004, pp. 597-598.
12. B. H. Lee, C. D. Young, R. Choi, J. H. Sim, G. Bersuker, C. Y. Kang, R. Harris, G. A. Brown, K. Matthews, S. C. Song, N. Moumen, J. Barnett, P. Lysaght, K. S. Choi, H. C. Wen, C. Huffman, H. Alshareef, P. Majhi, S. Gopalan, J. Peterson, P. Kirsh, H.-J. Li, J. Gutt, M. Gardner, H. R. Huff, P. Zeizoff, R. Murto, L. Larson, and C. Ramiller, "Intrinsic characteristics of fast transient charging effects (FCTE)," in IEDM Tech. Dig., 2004, pp. 859-862.