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Volumn 2003-January, Issue , 2003, Pages 183-188

Negative bias temperature instability of pMOSFETs with ultra-thin SiON gate dielectrics

Author keywords

[No Author keywords available]

Indexed keywords

ATOMS; DIELECTRIC MATERIALS; INTEGRATED CIRCUITS; MOSFET DEVICES; NEGATIVE TEMPERATURE COEFFICIENT; NITROGEN; RECONFIGURABLE HARDWARE; SILICON NITRIDE; THERMODYNAMIC STABILITY;

EID: 84955259235     PISSN: 15417026     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RELPHY.2003.1197743     Document Type: Conference Paper
Times cited : (26)

References (11)
  • 1
    • 0030646478 scopus 로고    scopus 로고
    • NBTI-channel hot carrier effects in pMOSFETs in advanced CMOS technologies
    • G. La Rosa, F. Guarin, A. Acovic, J. Lukatis, and E. Crabbe, "NBTI-channel hot carrier effects in pMOSFETs in advanced CMOS technologies", IRPS, p282, 1997
    • (1997) IRPS , pp. 282
    • La Rosa, G.1    Guarin, F.2    Acovic, A.3    Lukatis, J.4    Crabbe, E.5
  • 2
    • 0032633963 scopus 로고    scopus 로고
    • Bias temperature instability in scaled p+ polysilicon gate pMOSFET's
    • T. Yamamoto, K. Uwasawa, and T. Mogami, "Bias Temperature Instability in Scaled p+ Polysilicon Gate pMOSFET's", IEEE Trans. Elec. Dev., vol. 46, No. 5, p921, 1999
    • (1999) IEEE Trans. Elec. Dev. , vol.46 , Issue.5 , pp. 921
    • Yamamoto, T.1    Uwasawa, K.2    Mogami, T.3
  • 4
    • 0034446314 scopus 로고    scopus 로고
    • Very high performance 40 nm CMOS with ultra-thin nitride/Oxynitride stack gate dielectric and pre-doped dual poly-si gate electrodes
    • Q. Xiang, J. Jeon, P. Sachdey, B. Yu, K. C. Saraswat, and M.-R. Lin, "Very High Performance 40 nm CMOS with Ultra-thin Nitride/Oxynitride Stack Gate Dielectric and Pre-doped Dual Poly-Si Gate Electrodes", IEDM Tech. Dig., 2000
    • (2000) IEDM Tech. Dig.
    • Xiang, Q.1    Jeon, J.2    Sachdey, P.3    Yu, B.4    Saraswat, K.C.5    Lin, M.-R.6
  • 7
    • 0017493207 scopus 로고
    • Negative bias stress of MOS devices at high electric fields and degradation of MNOS devices
    • K. O. Jeppson and C. M. Svensson, "Negative bias stress of MOS devices at high electric fields and degradation of MNOS devices", J. Appl. Phys., 48, (5), p2004, 1977
    • (1977) J. Appl. Phys. , vol.48 , Issue.5 , pp. 2004
    • Jeppson, K.O.1    Svensson, C.M.2
  • 8
    • 36449005547 scopus 로고
    • Mechanism of negative-bias-temperature instability
    • 1
    • C. E. Blat, E. H. Nicollian, and E. H. Poindexter, "Mechanism of negative-bias-temperature instability", J. Appl. Phys., 69, (3), 1, p1772, 1991
    • (1991) J. Appl. Phys. , vol.69 , Issue.3 , pp. 1772
    • Blat, C.E.1    Nicollian, E.H.2    Poindexter, E.H.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.