Low-power branch target buffer for application-specific embedded processors

Proceedings - Euromicro Symposium on Digital System Design, DSD 2003

Volumn , Issue , 2003, Pages 158-165

  Petrov, P ^a   Orailoglu, A ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC CIRCUITS; ENERGY CONSUMPTION; SYSTEMS ENGINEERING;

EID: 26444473340     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DSD.2003.1231918     Document Type: Conference Paper

References (10)

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4. S. T. Pan, K. So and J. T. Rahmeh, "Improving the accuracy of dynamic branch prediction using branch correlation", in International Conference on Architectural Support for Programming Languages and Operating Systems, pp. 76-84, October 1992.
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6. L. H. Lee, J. Scott, B. Moyer and J. Arends, "Low-cost branch folding for embedded applications with small tight loops", in Proceedings of the 32nd International Symposium on Microarchitecture, pp. 103-111, November 1999.
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8. T. Austin, E. Larson and D. Ernst, "SimpleScalar: An infrastructure for computer system modeling", IEEE Computer, vol. 35, n. 2, pp. 59-67, February 2002.
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10. P. Shivakumar and N. Jouppi, "CACTI 3.0: An Integrated Cache Timing, Power and Area Model", Technical report, Western Research Lab, 2001.