Branch Target Buffer Design and Optimization

IEEE Transactions on Computers

Volumn 42, Issue 4, 1993, Pages 396-412

  Perleberg, Chris H ^a   Smith, Alan Jay ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Branch; branch problem; branch target buffer; cache memory; CPU design; CPU performance evaluation; pipeline; pipelining

Indexed keywords

COMPUTATIONAL COMPLEXITY; COMPUTER SYSTEMS; DESIGN; OPTIMIZATION; PERFORMANCE; PIPELINE PROCESSING SYSTEMS;

CACHE MEMORIES; CPU DESIGN; PIPELINING;

DIGITAL STORAGE;

EID: 0027578544     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.214687     Document Type: Article

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