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Volumn 3553, Issue , 2005, Pages 212-221

Hardware cost estimation for application-specific processor design

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER HARDWARE DESCRIPTION LANGUAGES; COSTS; DATABASE SYSTEMS; ESTIMATION;

EID: 26444467061     PISSN: 03029743     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1007/11512622_23     Document Type: Conference Paper
Times cited : (10)

References (11)
  • 1
    • 0031649808 scopus 로고    scopus 로고
    • Using transport triggered architectures for embedded processor design
    • Corporaal, H., Arnold, M.: Using transport triggered architectures for embedded processor design. Integrated Computer-Aided Eng. 5 (1998) 19-38
    • (1998) Integrated Computer-aided Eng. , vol.5 , pp. 19-38
    • Corporaal, H.1    Arnold, M.2
  • 4
    • 0032304488 scopus 로고    scopus 로고
    • Cycle-accurate macro-models for RT-level power analysis
    • Wu, Q., Qiu, Q., Pedram, M., Ding, C.S.: Cycle-accurate macro-models for RT-level power analysis. IEEE T. VLSI 6 (1998) 520-528
    • (1998) IEEE T. VLSI , vol.6 , pp. 520-528
    • Wu, Q.1    Qiu, Q.2    Pedram, M.3    Ding, C.S.4
  • 6
    • 0036542675 scopus 로고    scopus 로고
    • Cycle-accurate measurement and characterization with a case sudy of the ARM7TDMI
    • Chang, N., Kim, K., Lee, H.G.: Cycle-accurate measurement and characterization with a case sudy of the ARM7TDMI. IEEE T. VLSI 10 (2002) 146-154
    • (2002) IEEE T. VLSI , vol.10 , pp. 146-154
    • Chang, N.1    Kim, K.2    Lee, H.G.3
  • 8
    • 0033719421 scopus 로고    scopus 로고
    • Wattch: A framework for architectural-level power analysis and optimizations
    • Vancouver, BC, Canada
    • Brooks, D., Tiwari, V., Martonosi, M.: Wattch: A framework for architectural-level power analysis and optimizations. In: Proc. Int. Symp. Comput. Arch., Vancouver, BC, Canada (2000) 83-94
    • (2000) Proc. Int. Symp. Comput. Arch. , pp. 83-94
    • Brooks, D.1    Tiwari, V.2    Martonosi, M.3
  • 9
    • 0037249179 scopus 로고    scopus 로고
    • Evaluating integrated hardware-software optimizations using a unified energy estimation framework
    • Vijaykrishnan, N., Kandemir, M., Irwin, M.J., Kim, H.S., Ye, W., Duarte, D.: Evaluating integrated hardware-software optimizations using a unified energy estimation framework. IEEE T. Comput. 52 (2003) 59-76
    • (2003) IEEE T. Comput. , vol.52 , pp. 59-76
    • Vijaykrishnan, N.1    Kandemir, M.2    Irwin, M.J.3    Kim, H.S.4    Ye, W.5    Duarte, D.6
  • 10
    • 26444530745 scopus 로고    scopus 로고
    • A scalable methodology for cost estimation in a transformational high-level design space exploration environment
    • Paris, France
    • Gerlach, J., Rosenstiel, W.: A scalable methodology for cost estimation in a transformational high-level design space exploration environment. In: Proc. Design, Automation and Test in Europe, Paris, France (1998) 226-231
    • (1998) Proc. Design, Automation and Test in Europe , pp. 226-231
    • Gerlach, J.1    Rosenstiel, W.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.