A new framework for power estimation of embedded systems

Computer

Volumn 38, Issue 2, 2005, Pages 71-78

  Talarico, Claudio ^a   Rozenblit, Jerzy W ^a   Malhotra, Vinod ^b   Stritter, Albert ^c  

^a UNIVERSITY OF ARIZONA   (United States)

^b University of Hawaii at Manoa   (United States)

^c INFINEON TECHNOLOGIES AG   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

CACHE MEMORY; CMOS INTEGRATED CIRCUITS; COMPUTER PERIPHERAL EQUIPMENT; COMPUTER SIMULATION; DESIGN; MICROPROCESSOR CHIPS; TRANSISTORS; VLSI CIRCUITS;

POWER ESTIMATION; SYSTEM-ON-CHIP DESIGN;

EMBEDDED SYSTEMS;

EID: 15044351759     PISSN: 00189162     EISSN: None     Source Type: Trade Journal    
DOI: 10.1109/MC.2005.39     Document Type: Article

References (15)

1. A. Sangiovanni-Vincentelli and G. Martin, "Platform-Based Design and Software Design Methodology for Embedded systems," IEEE Design & Test of Computers, Nov./Dec. 2001, pp. 23-33.
2. V. Tiwari, S. Malik, and A. Wolfe, "Power Analysis of Embedded Software: A First Step toward Software Power Minimization," IEEE Trans. VLSI Systems, Dec. 1994, pp. 437-445.
3. S.M. Kang, "Accurate Simulation of Power Dissipation in VLSI Circuits," IEEE J. Solid-State Circuits, Oct. 1986, pp. 889-891.
4. T.H. Krodel, "PowerPlay - Fast, Dynamic Power Evaluation Based on Logic Simulation," Proc. 1991 IEEE Int'l Conf. Computer Design: VLSI in Computers & Processors (ICCD 91), IEEE CS Press, 1991, pp. 96-100.
5. S. Ravi, A. Raghunathan, and S. Chakradar, "Efficient RTL Power Estimation for Large Designs," Proc. 16th Int'l Conf. VLSI Design (VLSI03), IEEE CS Press, 2003, pp. 431-439.
6. M. Nemani and F.N. Najm, "High-Level Area and Power Estimation for VLSI Circuits," IEEE Trans. CAD of Integrated Circuits and Systems, June 1999, pp. 697-713.
7. R.Y. Chen, M.J. Irwin, and R.S. Bajwa, "Architecture-Level Power Estimation and Design Experiments," ACM Trans. Design Automation of Electronic Systems, Jan. 2001, pp. 50-66.
8. A.C.S. Beck et al., "CACO-PS: A General-Purpose Cycle-Accurate Configurable Power Simulator," Proc. 16th Symp. Integrated Circuits and Systems Design (SBCCI 03), IEEE CS Press, 2003, pp. 349-354.
9. C-T. Hsieh et al., "Profile-Driven Program Synthesis for Evaluation of System Power Dissipation," Proc. 34th Design Automation Conf., IEEE CS Press, 1997, pp. 576-581.
10. V. Dalal and C.P. Ravikumar, "Software Power Optimizations in an Embedded System," Proc. 14th Int'l Conf. VLSI Design (VLSI 01), IEEE CS Press, 2001, pp. 254-259.
11. C. Brandolese et al., "Static Power Modeling of 32-Bit Microprocessors," IEEE Trans. CAD Integrated Circuits and Systems Nov. 2002, pp. 1306-1316.
12. T. Givargis, F. Vahid, and J. Henkel, "Instruction-Based System-Level Power Evaluation of System-on-a-Chip Peripherals Cores,IEEE Trans. VLSI Systems, Dec. 2002, pp. 856-863.
13. M.B. Kambte and K. Ghose, "Energy-Efficiency of VLSI Caches: A Comparative Study," Proc. 10th Int'l Conf. VLSI Design: VLSI in Multimedia Applications (VLSI 97), IEEE CS Press, 1997, pp. 261-267.
14. K. Itoh, "Trends in Low-Voltage Embedded-RAM Technology," Proc. 23rd Int'l Conf. Microelectronics (MIEL 02), IEEE Press, 2002, pp. 497-501.
15. W. Fornaciari, D. Sciuto, and C. Silvano, "Power Estimation for Architectural Exploration of HW/SW Communication on System-Level Buses," Proc. 7th Int'l Workshop Hardware/Software Co-Design (CODES 99), IEEE CS Press, 1999, pp. 152-156.