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Volumn , Issue , 2005, Pages 217-220

High-resolution on-chip propagation delay detector for measuring within-chip variation

Author keywords

CMOS; Design automation; DLL; Propagation delay; Sub 100nm; Within chip variation

Indexed keywords

AUTOMATION; ELECTRIC POTENTIAL; INTEGRATED CIRCUIT LAYOUT; LOGIC CIRCUITS; VOLTAGE CONTROL;

EID: 25844487780     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/icicdt.2005.1502634     Document Type: Conference Paper
Times cited : (4)

References (12)
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  • 7
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    • High-resolution on-chip propagation delay detector for measuring within-chip and chip-to-chip variation
    • Takashi Matsumoto, "High-Resolution On-Chip Propagation Delay Detector for Measuring Within-Chip and Chip-to-Chip Variation," IEEE Symp. on VLSI Circuits 2004.
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    • Matsumoto, T.1
  • 8
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    • John G. Maneatis, "Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques," IEEE J. Solid-State Circuits, vol. 31, no. 11, pp. 1723-1732, Nov. 1996.
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  • 9
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  • 11
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.