Low error fixed-width modified Booth multiplier

IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation

Volumn 2002-January, Issue , 2002, Pages 45-50

  Cho, K J ^a   Lee, K C ^a   Chung, J G ^a   Parhi, K K ^b  

^a Chonbuk National University   (South Korea)

^b BROADCOM CORPORATION   (United States)

Author keywords

Adders; Circuit simulation; Digital signal processing; Error compensation; Finite wordlength effects; Linear regression; Quantization; Signal generators; Statistical analysis; USA Councils

Indexed keywords

ADDERS; CIRCUIT SIMULATION; DIGITAL SIGNAL PROCESSING; ERRORS; LINEAR REGRESSION; MULTIPLYING CIRCUITS; QUANTIZATION (SIGNAL); SIGNAL GENERATORS; SIGNAL PROCESSING; STATISTICAL METHODS;

ERROR COMPENSATION METHODS; FINITE WORD LENGTH EFFECTS; FIXED WIDTH MULTIPLIER; MODIFIED BOOTH MULTIPLIERS; MULTIPLIER COEFFICIENT; QUANTIZATION; QUANTIZATION ERRORS; USA COUNCILS;

ERROR COMPENSATION;

EID: 2542438450     PISSN: 15206130     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SIPS.2002.1049683     Document Type: Conference Paper

References (6)

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