The problem of optimal placement of Sub-Resolution Assist Features (SRAF)

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 5754, Issue PART 3, 2005, Pages 1417-1429

  Mukherjee, Maharaj ^a   Mansfield, Scott ^a   Liebmann, Lars ^a   Lvov, Alexey ^a   Papadopoulou, Evanthia ^a   Lavin, Mark ^a   Zhao, Zengqin ^a  

^a IBM RESEARCH   (United States)

Author keywords

Design Rule Checking (DRC); Geometric Optimization; Lithographic process; Mask Rule Checking (MRC); Optical Proximity Correction (OPC); Process Window; Resolution Enhancement Techniques (RET); Sub Resolution Assist Features (SRAF); Voronoi Diagram

Indexed keywords

GEOMETRICAL OPTICS; LITHOGRAPHY; OPTIMIZATION; PROBLEM SOLVING;

DESIGN RULE CHECKING (DRC); GEOMETRIC OPTIMIZATION; LITHOGRAPHIC PROCESS; MASK RULE CHECKING (MRC); OPTICAL PROXIMITY CORRECTION (OPC); PROCESS WINDOW; RESOLUTION ENHANCEMENT TECHNIQUES (RET); SUB RESOLUTION ASSIST FEATURES (SRAF); VORONOI DIAGRAM;

OPTICAL RESOLVING POWER;

EID: 25144445271     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.599884     Document Type: Conference Paper

References (9)

1. L. Liebmann and S. Mansfield, "Method of incorporating sub resolution assist features in a photomask layout", US Patent 6413683, 2002.
2. J. Bruce, M. Cross, L. Liebmann, S. Mansfield, and A. McGuire, "Assist - Features - Challenges and Opportunities", ARCH Microlithography Symp., 2000
3. S. Mansfield, L. Liebmann, A. Molless and A. K. Wong, "Lithographic Comparison of Assist Feature Design Strategies", in Proc. SPIE, vol. 4000, 2000.
4. J. F. Chen, K. Wampler and T. L. Laidig, "Optical proximity correction methods for intermediate pitch features using sub-resolution scattering bars on a mask", US Patent 5821014, 1998.
5. L. Liebmann, J. A. Bruce, W Chu, M. Cross, I. Graur, J. Crueger, W. Leipold, S. Mansfield, A. McGuire, and D. Sundling, "Optimizing style options for sub-resolution assist features", in Proc. SPIE, vol. 4346, 2001
6. S. Mansfield, L. Liebmann, S. Butt, and H. Haffner, "Semiconductor device fabrication using a photomask with assist features" US Patent 6421820, 2003.
7. "Critical Area Computation via Voronoi diagrams", E. Papadopoulou and D.T. Lee, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 18, No. 4, April 1999, 463-474.
8. "The L∞ Voronoi Diagram of Segments and VLSI Applications", E. Papadopoulou and D.T. Lee, International Journal of Computational Geometry and Applications, vol. 11, No. 5, 2001, 503-528.
9. "CAE: Critical Area Extraction", Internal IBM tool for the prediction of yield of VLSI chips, Department of Electronic Design Automation, IBM Microelectronics Division, Burlington, VT. Initial patents: US 6178539, US 6317859.