The L∞ Voronoi diagram of segments and VLSI applications

International Journal of Computational Geometry and Applications

Volumn 11, Issue 5, 2001, Pages 503-528

  Papadopoulou, Evanthia ^a   Lee, D T ^b,c  

^a IBM T J WATSON RESEARCH CENTER   (United States)

^b INSTITUTE OF INFORMATION SCIENCE   (Taiwan)

^c University of Illinois at Chicago   (United States)

Author keywords

Algorithmic degree; Critical area; L metric; VLSI layout; Voronoi diagram

Indexed keywords

EID: 0035605053     PISSN: 02181959     EISSN: None     Source Type: Journal    
DOI: 10.1142/S0218195901000626     Document Type: Article

References (28)

1. O. Aichholzer, F. Aurenhammer, "Straight Skeletons for general Polygonal Figures in the Plane", Proc. 2nd Int. Computing and Combinatorics Conference, 1996 Lecture Notes in Computer Science 1090, 117-126.
2. F. Aurenhammer, "Voronoi diagrams: A survey of a fundamental geometric data structure," ACM Comput. Survey, 23 1991, 345-405.
3. F. Aurenhammer and R. Klein, "Voronoi Diagrams" chapter 18, Textbook on Computational Geometry, J. Sack and G. Urrutia (eds), Elsevier Science Publishing 2000, 201-290.
4. F. Avnaim, J.D. Boissonnat, O. Devillers, F. Preparata, M. Yvinec, "Evaluating signs of determinants using single precision arithmetic", Algorithmica, 17 1997, 11-132.
5. J.D. Boissonnat, F. Preparata, "Robust plane sweep for intersecting segments", SIAM J. Computing, to appear.
6. C. Burnikel, "Exact Computation of Voronoi diagrams and Line Segment Intersections", Ph.D. Dissertation, Universität des Saarlandes, Saarbrücken Germany, March 1996.
7. C. Burnikel, K, Mehlhorn S. Schirra, "How to compute the Voronoi Diagram of Line Segments: Theoretical and Experimental Results" Proc. 2nd Annu. European Symp. on Algorithms, 1994, LNCS 855, 227-239.
8. k," IBM J. Research and Development, Nov. 1979, 696-699.
9. F. Dehne and R. Klein, "The Big Sweep": On the power of the Wavefront Approach to Voronoi Diagrams", Algorithmica(1997), 17, 19-32.
10. A.V. Ferris-Prabhu, "Modeling the Critical Area in Yield Forecast", IEEE J. of Solid State Circuits, vol. SC-20, No4, Aug. 1985, 874-878
11. A.V. Ferris-Prabhu, "Defect size variations and their effect on the critical area of VLSI devices", IEEE J. of Solid State Circuits, vol. SC-20, No4, Aug. 1985, 878-880.
12. S. J. Fortune, "A sweepline algorithm for Voronoi diagrams", Algorithmica, 2, 1987, 153-174.
13. S. J. Fortune, "Numerical Stability of Algorithms for 2-d Delaunay triangulations", International J. Comput. Geom. Applic., 5(1), 1995, 193-213.
14. I. Koren, "The effect of scaling on the yield of VLSI circuits", Yield Modeling and defect Tolerance in VLSI circuits W.R. Moore, W. Maly, and A. Strojwas Eds., Bristol UK: Adam-Hilger Ltd., 1988, 91-99
15. G. Liotta, F.P. Preparata, and R. Tamassia, "Robust Proximity Queries: An illustration of degree-driven algorithm design," SIAM Journal on Computing, 28, 3, 1998, 864-889.
16. W. Maly, "Computer Aided Design for VLSI Circuit Manufacturability", Proc. IEEE, Feb. 90, 356-392.
17. W. Maly, and J. Deszczka, "Yield Estimation Model for VLSI Artwork Evaluation", Electron Lett. vol 19, no.6, 226-227, March 1983
18. S. N. Meshkat and C. M. Sakkas. "Voronoi diagram for multiply-connected polygonal domains II: Implementation and application", IBM J. of Research and Development, Vol. 31, No. 3, May 1987
19. E. Papadopoulou and D.T. Lee, "Critical Area computation via Voronoi diagrams", IEEE Trans. on Computer-Aided Design, vol. 18, No. 4, April 1999, 463-474.
20. J. Pineda de Gyvez, C. Di, "IC Defect Sensitivity for Footprint-Type Spot Defects", IEEE Trans. on Computer-Aided Design, vol. 11, no 5, 638-658, May 1992
21. K. Sugihara, Y. Ooishi, and T. Imai, "Topology oriented approach to robustness and its applications to several Voronoi-diagram algorithms. In Proc. 2nd Canad. Conf. Comput. Geom., pages 36-39, 1990
22. V. Srinivasan Personal Communication.
23. V. Srinivasan, L.R. Nackman, "Voronoi diagram for multiply-connected polygonal domains II: Algorithm", IBM Journal of Research and Development, Vol. 31, No. 3, May 1987
24. V. Srinivasan, L.R. Nackman, J.M. Tang, and S.N. Meshkat, "Automatic Mesh Generation Using the Symmetric Axis Transformation of Polygonal Domains", Proceedings of the IEEE, Vol. 80, No. 9, Sept. 1992, 1485-1501.
25. C.H. Stapper, "Modeling of Defects in integrated circuits photolithographic patterns", IBM J. Research and Development, vol.28, no.4, 461-475, 1984.
26. C. H. Stapper and R. J. Rosner, "Integrated Circuit Yield Management and Yield Analysis: Development and Implementation" IEEE Trans. on Semiconductor Manufacturing Vol. 8, No.2, 1995, 95-101.
27. I. A. Wagner and I. Koren, "An Interactive VLSI CAD Tool for Yield Estimation", IEEE Trans. on Semiconductor Manufacturing Vol. 8, No.2, 1995, 130-138.
28. H. Walker and S.W. Director, "VLASIC: A yield simulator for integrated circuits", IEEE Trans. on Computer-Aided Design, vol. CAD-5, no 4, 541-556, Oct. 1986.