Partial pre-applied underfill for assembly and reliability of Pb-free CSPs

Proceedings - Electronic Components and Technology Conference

Volumn 1, Issue , 2005, Pages 223-227

  Morganelli, Paul ^a   Shah, Jayesh ^a   Wheelock, Brian ^a   Mohan, Vinod ^a   Laffey, Matthew ^a  

^a Emerson and Cuming Company   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

PRE-APPLIED UNDERFILLS; REFLOW; STANDOFF GAP;

ARRAYS; COATINGS; DRYING; IMPACT RESISTANCE; PRINTED CIRCUIT BOARDS; REINFORCEMENT;

CHIP SCALE PACKAGES;

EID: 24644459474     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. th Electronic Components and Technology Conf, Las Vegas, NV, June 2004, pp. 770-774
2. Zhang, Zhuquing. et al, "Study on B-stage properties of wafer level underfills", J. Adhesion Sci. Tchnol., Vol. 18, No. 3, (2004) pp. 361-380, and references cited therein.
3. th Electronic Components and Technology Conf, Las Vegas, NV, June 2004, pp. 170-174.
4. Hannan, N. et at. International Patent Application WO 02/093595 A2
5. Danvir, J. et al. US Pat. Appl. 2004/0169275
6. rd Electronic Components and Technology Conf, Las Vegas, NV, June 2002, pp. 978-982