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Volumn 18, Issue 3, 2004, Pages 361-380

Study on B-stage properties of wafer level underfills

Author keywords

B stage; Cure kinetics; Flip chip; Underfill; Wafer level

Indexed keywords

CURING; INTEGRATED CIRCUIT MANUFACTURE; JOINTS (STRUCTURAL COMPONENTS); STRESS ANALYSIS; SUBSTRATES; SURFACE MOUNT TECHNOLOGY; THERMAL EXPANSION; COAGULATION; DIAMOND CUTTING TOOLS; GELATION;

EID: 2342464934     PISSN: 01694243     EISSN: None     Source Type: Journal    
DOI: 10.1163/156856104773635472     Document Type: Article
Times cited : (12)

References (12)
  • 5
    • 2342620856 scopus 로고    scopus 로고
    • US Patent No. 6,180,696
    • C. P. Wong and S. H. Shi, US Patent No. 6,180,696 (2001).
    • (2001)
    • Wong, C.P.1    Shi, S.H.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.