Integration of a low stress photopatternable silicone into a Wafer Level Package

Proceedings - Electronic Components and Technology Conference

Volumn 1, Issue , 2004, Pages 170-174

  Gardner, G ^a   Harkness, B ^a   Ohare, E ^a   Meynen, H ^b   Bulcke, M Vanden ^c   Gonzalez, M ^c   Beyne, E ^c  

^a DOW CORNING CORPORATION   (United States)

^b Dow Corning SA Belgium   (Belgium)

^c IMEC   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUITS; MICROELECTRONICS; PRINTED CIRCUIT BOARDS; SILICON WAFERS; SILICONES; SOLDERED JOINTS; THERMAL CYCLING; THERMAL EXPANSION;

LOW STRESS PHOTOPATTERNABLE SILICONE; PLASMA CLEANING; WAFER LEVEL PACKAGE;

ELECTRONICS PACKAGING;

EID: 4544273683     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

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