-
1
-
-
0003304960
-
A root cause failure mechanism for solder joint integrity of electroless Nickel/immersion gold surface finishes
-
Paper no. S18-5, March 14-18
-
Nicholas Biunno, "A Root Cause Failure Mechanism for Solder Joint Integrity of Electroless Nickel/Immersion Gold Surface Finishes," Proc. IPC Printed Circuits Expo1999, Paper no. S18-5, March 14-18, 1999.
-
(1999)
Proc. IPC Printed Circuits Expo1999
-
-
Biunno, N.1
-
2
-
-
0032630767
-
Effects of electroless Ni/immersion au plating parameters on PBGA solder joint attachment reliability
-
June 1-4
-
Zequn Mei, Pat Johnson, Matt Kaufmann, Ali Eslambolchi, "Effects of Electroless Ni/Immersion Au Plating Parameters on PBGA Solder Joint Attachment Reliability," Proc. 49th Electronic Component and Technology Conference, 125-134, June 1-4, 1999.
-
(1999)
Proc. 49th Electronic Component and Technology Conference
, pp. 125-134
-
-
Mei, Z.1
Johnson, P.2
Kaufmann, M.3
Eslambolchi, A.4
-
3
-
-
29244443126
-
Black pad defect: Influence of geometry and other factors
-
Rosemont, IL, Sept.
-
J. A. Roepsch, R. F. Champaign, B. M. Waller, "Black Pad Defect: Influence of Geometry and Other Factors", Proc. Of SMTA International, Rosemont, IL, Sept. 2003.
-
(2003)
Proc. of SMTA International
-
-
Roepsch, J.A.1
Champaign, R.F.2
Waller, B.M.3
-
4
-
-
0034822476
-
Development of electroless Ni/Au plated build-up flip chip package with highly reliable solder joints
-
K. Yokomine, N. Shimizu, Y. Miyamoto, Y. Iwata, D. Love and K. Newman, "Development of Electroless Ni/Au Plated Build-Up Flip Chip Package with Highly Reliable Solder Joints", Proc. of Engineering Components Technology Conf. (ECTC), 2001.
-
(2001)
Proc. of Engineering Components Technology Conf. (ECTC)
-
-
Yokomine, K.1
Shimizu, N.2
Miyamoto, Y.3
Iwata, Y.4
Love, D.5
Newman, K.6
-
5
-
-
0009616246
-
Are you in control of your electroless Nickel/immersion gold process?
-
Miami, Fl, Sept.
-
K. Johal and J. Brewer, "Are you in Control of your Electroless Nickel/Immersion Gold Process?", Proc. Of IPC Works, No. S03-3, Miami, Fl, Sept. 2000.
-
(2000)
Proc. of IPC Works
, vol.S03-3
-
-
Johal, K.1
Brewer, J.2
-
6
-
-
24644507164
-
Flexure induced failure of BGA solder joints
-
Sept.
-
K. Lei, J. LLinas, and M. Gwaltney, "Flexure induced failure of BGA solder joints", Proc. Of SMTAI, Sept. 1999.
-
(1999)
Proc. of SMTAI
-
-
Lei, K.1
Llinas, J.2
Gwaltney, M.3
-
7
-
-
0001958112
-
Reliability performance and failure mode of high I/O thermally enhanced ball grid array packages
-
Austin, TX, October 19-21
-
R. J. Coyle, T. I. Ejim, A. Holliday, P. P.Solan, and J. K. Dorey, "Reliability Performance and Failure Mode of High I/O Thermally Enhanced Ball Grid Array Packages," Proc. 23th IEMT, Austin, TX, 323-332, October 19-21, 1998.
-
(1998)
Proc. 23th IEMT
, pp. 323-332
-
-
Coyle, R.J.1
Ejim, T.I.2
Holliday, A.3
Solan, P.P.4
Dorey, J.K.5
-
8
-
-
0036292654
-
Failure mechanism of brittle solder joint fracture in the presence of Electroless Nickel Immersion Gold (ENIG) Interface
-
Deepak Goyal, T. Lane, P. Kinzie, C. Panichas, K. M. Chong, and O. Villalobos, "Failure Mechanism of Brittle Solder Joint Fracture in the Presence of Electroless Nickel Immersion Gold (ENIG) Interface", Proc. of Engineering Components Technology Conf. (ECTC), 2002.
-
(2002)
Proc. of Engineering Components Technology Conf. (ECTC)
-
-
Goyal, D.1
Lane, T.2
Kinzie, P.3
Panichas, C.4
Chong, K.M.5
Villalobos, O.6
-
12
-
-
24644464733
-
Characterization of PWB flexural loading using strain gages
-
San Jose, CA, March
-
K. Newman, "Characterization of PWB Flexural Loading Using Strain Gages", Presented at Sun Microsystems Strain Gage Test Summit, San Jose, CA, March 2004.
-
(2004)
Sun Microsystems Strain Gage Test Summit
-
-
Newman, K.1
-
13
-
-
0034829982
-
Reliability study of high-pin-count flip chip BGA
-
Y. Li, J. Xie, T. Verma, and V. Wang, "Reliability Study of High-Pin-Count Flip chip BGA", Proc. of Engineering Components Technology Conf. (ECTC), 2001.
-
(2001)
Proc. of Engineering Components Technology Conf. (ECTC)
-
-
Li, Y.1
Xie, J.2
Verma, T.3
Wang, V.4
-
16
-
-
84861245914
-
-
Patent "Method for measuring interconnect and board level reliability using a Programmable Logic Device"
-
R. Wu, J. Barton, B., Euzent, A. Pannikkat, T. Jonsson, V. Mahadev, Patent "Method for measuring interconnect and board level reliability using a Programmable Logic Device"
-
-
-
Wu, R.1
Barton, J.2
Euzent, B.3
Pannikkat, A.4
Jonsson, T.5
Mahadev, V.6
|