Identifying and Addressing the Challenges of Logic and Memory Integration

Journal of Japan Institute of Electronics Packaging

Volumn 7, Issue 5, 2004, Pages 401-404

  Mitchell, Craig ^a  

^a Tessera Inc   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 24644474635     PISSN: 13439677     EISSN: 1884121X     Source Type: Journal    
DOI: 10.5104/jiep.7.401     Document Type: Article

References (5)

1. G. Raskin: “Integration Challenges for Wireless IC Handset Makers”, 3D Packaging Symposium, July 15, 2003.
2. J. Vardaman: “Stacked CSPs: Market and Technology Developments”, 10th Annual International KGD Packaging & Test Workshop, September 8-10, 2003.
3. C. E. Bauer, and J. Riley: “Multichip Packaging: Business and Logistical Issues”, Advanced Packaging, p. 29, January 2003.
4. L. Smith: “Applications and Advances in Chip Scale Packaging Stacking”, IMAPS Advanced Technology Workshop on Advanced 3D Packaging, March 12, 2003.
5. S. Greathouse: “3D Stacked Package Technology, Facing Tomorrow's Needs Today”, 3D Packaging Symposium, July 15, 2003.