Effect of wafer level packaging, silicon substrate and board material on gigabit board-silicon-board data transmission

Proceedings - Electronic Components and Technology Conference

Volumn 2, Issue , 2004, Pages 1506-1512

  Kim, W ^a   Madhavan, R ^a   Mao, J ^a   Choi, J ^a   Choi, S ^b   Ravi, D ^a   Sundaram, V ^a   Sankararaman, S ^a   Gupta, P ^a   Zhang, Z ^a   Lo, G ^a,c   Swaminathan, M ^a   Tummala, R ^a   Sitaraman, S ^a,c   Wong, C P ^a   Iyer, M ^a,c   Rotaru, M ^a,c   Tay, A ^d  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^b Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

^c INSTITUTE OF MICROELECTRONICS   (Singapore)

^d NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; DATA COMMUNICATION SYSTEMS; ELECTRIC LINES; INTEGRATED CIRCUITS; MICROPROCESSOR CHIPS; PRINTED CIRCUIT BOARDS; SIGNAL PROCESSING; SILICON;

GIGABIT; SIGNAL INTEGRITY; SILICON SUBSTRATE; WAFER LEVEL PACKAGING;

ELECTRONICS PACKAGING;

EID: 10444261949     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)

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