Product level verification of gate oxide reliability projections using DRAM chips

IEEE International Reliability Physics Symposium Proceedings

Volumn 2003-January, Issue , 2003, Pages 385-390

  Vollertsen, R P ^a   Nierle, K ^b   Wu, E Y ^c   Wen, S ^b  

^a INFINEON TECHNOLOGIES AG   (Germany)

^b INFINEON TECHNOLOGIES   (United States)

^c IBM MICROELECTRONICS   (United States)

Author keywords

DRAM; Gate oxide reliability; Lifetime model; Oxide breakdown; Product correlation; Projection

Indexed keywords

CIRCUIT SIMULATION; DYNAMIC RANDOM ACCESS STORAGE; GATES (TRANSISTOR); RELIABILITY;

BREAKDOWN RESISTANCE; CURRENT DEGRADATION; DEVICE CHARACTERISTICS; GATE OXIDE RELIABILITY; LIFETIME MODELS; OXIDE BREAKDOWN; PROJECTION; STANDARD PRODUCTS;

RECONFIGURABLE HARDWARE;

EID: 2442560763     PISSN: 15417026     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RELPHY.2003.1197778     Document Type: Conference Paper

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