Wrapper-based bus implementation techniques for performance improvement and cost reduction

IEEE Journal of Solid-State Circuits

Volumn 39, Issue 5, 2004, Pages 804-817

  Anjo, Kenichiro ^a   Okamura, Atsushi ^a   Motomura, Masato ^a  

^a RENESAS TECHNOLOGY CORP   (Japan)

Author keywords

Bus protocols; Computer architecture; Computer performance; Integrated circuit interconnections; On chip buses

Indexed keywords

CMOS INTEGRATED CIRCUITS; INTERCONNECTION NETWORKS; INTERFACES (COMPUTER); INTERNET; NETWORK PROTOCOLS;

BUS PROTOCOLS; COMPUTER PERFORMANCE; ON CHIP BUSES; SYSTEM ON CHIP (SOC) DESIGNS;

MICROPROCESSOR CHIPS;

EID: 2442530077     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2004.826325     Document Type: Article

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