Design guidelines and process quality improvement for treatment of device variations in an LSI chip

IEICE Transactions on Electronics

Volumn E88-C, Issue 5, 2005, Pages 788-794

  Aoki, Masakazu ^a,b   Ohkawa, Shin Ichi ^a,c   Masuda, Hiroo ^a  

^a SEMICONDUCTOR TECHNOLOGY ACADEMIC RESEARCH CENTER   (Japan)

^b TOKYO UNIVERSITY OF SCIENCE   (Japan)

^c RENESAS TECHNOLOGY CORP   (Japan)

Author keywords

Correlation length; Fitting function; Random variation; Systematic variation; Within die parameter variation

Indexed keywords

ELECTRIC RESISTANCE; LEAST SQUARES APPROXIMATIONS; MICROPROCESSOR CHIPS; POLYNOMIALS; POLYSILICON; QUALITY CONTROL; RANDOM PROCESSES; TRANSISTORS;

CORRELATION LENGTH; FITTING FUNCTION; RANDOM VARIATIONS; SYSTEMATIC VARIATIONS; WITHIN-DIE PARAMETER VARIATIONS;

LSI CIRCUITS;

EID: 24144464519     PISSN: 09168524     EISSN: None     Source Type: Journal    
DOI: 10.1093/ietele/e88-c.5.788     Document Type: Conference Paper

References (8)

1. Proc. International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU 2002), Monterey, CA, Dec. 2002.
2. D. Boning, J. Panganiban, K. Gonzalez-Valentin, S. Nassif, C. MacDowell, A. Gattiker, and F. Liu, "Test structures for delay variability," Proc. International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU 2002), p. 109, Monterey, CA, Dec. 2002.
3. S. Ohkawa, M. Aoki, and H. Masuda, "Analysis and characterization of device variations in an LSI chip using an integrated Device Matrix Array," Proc. ICMTS, pp.70-75, March 2003.
4. M.J.M. Pelgrom, A.C.J. Duinmaijer, and A.P.G. Welbers, "Matching properties of MOS transistors," IEEE J. Solid-State Circuits, vol.24, no.5, pp. 1433-1440, Oct. 1989.
5. D. Burnett, K. Erington, C. Subramanian, and K. Baker, "Implication of fundamental threshold voltage variations for high-density SRAM and logic circuits," Symp. VLSI Technology, Technical Digest, pp.15-16, June 1994.
6. A. Agarwal, D. Blaauw, V. Zolotov, S. Sundareswaran, M. Zhao, K. Gala, and R. Panda, "Statistical delay computation considering spatial correlations," Proc. ASP-DAC, pp.271-276, Jan. 2003.
7. J.C. Chen, D. Sylvester, C. Hu, H. Aoki, S. Nakagawa, and S.-Y. Oh, "An on-chip, interconnect capacitance characterization method with sub-femto-farad resolution," Proc. ICMTS, pp.77-80, March 1997.
8. B.E. Stine, D.S. Boning, and J.E. Chung, "Analysis and decomposition of spatial variation in integrated circuit processes and devices," IEEE Trans. Semicond. Manuf., vol.10, no.1, pp.24-41, Feb. 1997.