Achieving structural and composable modeling of complex systems

International Journal of Parallel Programming

Volumn 33, Issue 2-3, 2005, Pages 81-101

  August, David I ^a   Malik, Sharad ^a   Peh, Li Shiuan ^a   Pai, Vijay ^b   Vachharajani, Manish ^c   Willmann, Paul ^d  

^a Princeton University   (United States)

^b PURDUE UNIVERSITY   (United States)

^c University of Colorado at Boulder   (United States)

^d Rice University   (United States)

Author keywords

Liberty simulation environment; Structural simulation

Indexed keywords

AUTOMATION; COMPUTER HARDWARE; COMPUTER SIMULATION; COMPUTER SYSTEMS PROGRAMMING; MACHINE DESIGN; PARALLEL PROCESSING SYSTEMS;

COMPONENT LIBRARIES; INTUITIVE FASHION; MODELING SYSTEM; NOVEL DESIGN;

LARGE SCALE SYSTEMS;

EID: 24044461043     PISSN: 08857458     EISSN: None     Source Type: Journal    
DOI: 10.1007/s10766-005-3569-3     Document Type: Article

References (33)

1. R. Desikan, D. Burger, and S. W. Keckler, Measuring Experimental Error in Micro-processor Simulation, Proceedings of the 28th International Symposium on Computer Architecture (July 2001).
2. H. W. Cain, K. M. Lepak, B. A. Schwartz, and M. H. Lipasti, Precise and Accurate Processor Simulation, Proceedings of the Fifth Workshop on Computer Architecture Evaluation using Commercial Workloads (February 2002).
3. J. Gibson, R. Kunz, D. Ofelt, M. Horowitz, J. Hennessy, and M. Heinrich, FLASH vs. (Simulated) FLASH: Closing the Simulation Loop, Proceedings of the 9th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), pp. 49-58 (November 2000).
4. V. S. Pai, P. Ranganathan, and S. V. Adve, RSIM Reference Manual, Version 1.0, Electrical and Computer Engineering Department, Rice University (August 1997), technical Report 9705.
5. C. J. Hughes, V. S. Pai, P. Ranganathan, and S. V. Adve, Rsim: Simulating Shared-Memory Multiprocessors with ILP Processors, IEEE Computer, 35(2):40-49 (February 2002).
6. D. Burger and T. M. Austin, The SimpleScalar Tool Set Version 2.0, Technical Report 97-1342, Department of Computer Science, University of Wisconsin-Madison (June 1997).
7. S. Önder and R. Gupta, Automatic Generation of Microarchitecture Simulators, Proceedings of the IEEE International Conference on Computer Languages, pp. 80-89 (May 1998).
8. S. Pees, A. Hoffmann, V. Živojnović, and H. Meyr, LISA - Machine Description Language for Cycle-Accurate Models of Programmable DSP Architectures, Proceedings of the ACM/IEEE Design Automation Conference (DAC), pp. 933-938 (1999).
9. C. Siska, A Processor Description Language Supporting Retargetable Multi-Pipeline DSP Program Development Tools, Proceedings of the 11th International Symposium on System Synthesis (ISSS) (December 1998).
10. A. Halambi, P. Grun, V. Ganesh, A. Khare, N. Dutt, and A. Nicolau, EXPRESSION: A Language for Architecture Exploration Through Compiler/Simulator Retargetability, Proceedings of the European Conference on Design, Automation and Test (DATE) (March 1999).
11. J. Buck, S. Ha, E. A. Lee, and D. G. Messerschmitt, Ptolemy: A Framework for Simulating and Prototyping Heterogeneous Systems, International Journal in Computer Simulation, 4:155-182 (1994).
12. Open SystemC Initiative (OSCI), Functional Specification for SystemC 2.0 (2001), URL http://www.systemc.org, http://www.systemc.org.
13. J. Emer, P. Ahuja, E. Borch, A. Klauser, C.-K. Luk, S. Manne, S. S. Mukherjee, H. Patil, S. Wallace, N. Binkert, R. Espasa, and T. Juan, Asim: A Performance Model Framework, IEEE Computer, 0018-9162:68-76 (February 2002).
14. P. Mishra, N. Dutt, and A. Nicolau, Functional Abstraction Driven Design Space Exploration of Heterogeneous Programmable Architectures, Proceedings of the International Symposium on System Synthesis (ISSS), pp. 256-261 (October 2001), URL citeseer.nj.nec.com/506348.html.
15. M. Vachharajani, N. Vachharajani, D. A. Penry, J. A. Blome, and D. I. August, Microarchitectural Exploration with Liberty, Proceedings of the 35th International Symposium on Microarchitecture, pp. 271-282 (November 2002).
16. M. Vachharajani, Microarchitectural Modeling for Design-space Exploration, Ph.D. thesis, Department of Electrical Engineering, Princeton University, Princeton, NJ USA (November 2004).
17. H.-S. Wang, X. Zhu, L.-S. Peh, and S. Malik, Orion: A Power-Performance Simulator of Interconnection Networks, Proceedings of the 35th International Symposium on Microarchitecture (November 2002).
18. P. Murthy, Modeling and Design of Reactive Systems (1997), presentation. URL: http://ptolemy.eecs.berkeley.edu/presentations/97/rasspfinal.pdf.
19. E. A. Lee and A. Sangiovanni-Vincentelli, Comparing Models of Computation, Proceedings of ICCAD (November 1996).
20. A. Girault, B. Lee, and E. A. Lee, Hierarchical Finite State Machines with Multiple Concurrency Models, IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, 18(6):742-760 (June 1999).
21. D. Penry and D. I. August, Optimizations for a Simulator Construction System Supporting Reusable Components, Proceedings of the 40th Design Automation Conference (June 2003).
22. N. Eisley and L.-S. Peh, High-Level Power Analysis of On-Chip Netowrks, Proceedings of 7th International Conference on Compilers, Architectures and Synthesis for Embedded Systems (September 2004).
23. B. M. Beckmann and D. Wood, Transmission Line Caches, Proceedings of the International Symposium on Microarchitecture, pp. 43-55 (December 2003).
24. T. T. Ye, L. Benini, and G. D. Micheli, Packetized On-Chip Interconnect Communication Analysis for MPSoC, Proceedings of Design Automation and Test in Europe, pp. 344-349 (March 2003).
25. H.-S. Wang, L.-S. Peh, and S. Malik, High-Level Power Analysis of On-Chip Netowrks, In IEEE Micro, Vol. 24, No. 1, (Best of Hot Interconnects 10) (February 2003).
26. X. Chen and L.-S. Peh, Leakage Power Modeling and Optimization of Interconnection Networks, Proceedings of the International Symposium on Low Power and Energy Design, pp. 90-95 (August 2003).
27. L. Shang, L.-S. Peh, A. Kumar, and N. K. Jha, Thermal Modeling, Characterization and Optimization of On-Chip Networks, Proceedings of the 37th International Symposium on Microarchitecture (December 2004).
28. D. J. Sorin, V. S. Pai, S. V. Adve, M. K. Vernon, and D. A. Wood, Analytic Evaluation of Shared-Memory Systems with ILP Processors, Proceedings of the 25th Annual International Symposium on Computer Architecture, pp. 380-391 (June 1998).
29. P. Crowley, M. Fiuczynski, J.-L. Baer, and B. Bershad, Characterizing Processor Architectures for Programmable Network Interfaces, Proceedings of the 14th International Conference on Supercomputing, pp. 54-65 (May 2000).
30. K. Mackenzie, W. Shi, A. McDonald, and I. Ganev, An Intel IXP1200-based Network Interface, Proceedings of the Second Workshop on Novel Uses of System Area Networks (SAN-2) (2003).
31. P. Willmann, M. Brogioli, and V. S. Pai, Spinach: A Liberty-based Simulator for Programmable Network Interface Architectures, Proceedings of the ACM SIGPLAN/SIGBED 2004 Conference on Languages, Compilers, and Tools for Embedded Systems, pp. 20-29, ACM Press (July 2004).
32. Alteon Networks, Tigon/PCI Ethernet Controller (August 1997), revision 1.04.
33. Alteon WebSysterns, Gigabit Ethernet/PCI Network Interface Card: Host/ NIC Software Interface Definition (July 1999), revision 12.4.13.