Parallel CRC realization

IEEE Transactions on Computers

Volumn 52, Issue 10, 2003, Pages 1312-1319

  Campobello, Giuseppe ^a   Patané, Giuseppe ^a   Russo, Marco ^b  

^a UNIVERSITY OF MESSINA   (Italy)

^b UNIVERSITY OF CATANIA   (Italy)

Author keywords

Digital logic; Error detection; FPGA; LFSR; Parallel CRC; VHDL; VLSI

Indexed keywords

CODES (SYMBOLS); DIGITAL ARITHMETIC; FIELD PROGRAMMABLE GATE ARRAYS; LOGIC CIRCUITS; PARALLEL PROCESSING SYSTEMS; POLYNOMIALS; RECURSIVE FUNCTIONS; SHIFT REGISTERS; VLSI CIRCUITS;

CYCLIC REDUNDANCY CHECK; DIGITAL LOGIC; FRAME CHECK SEQUENCE; LINEAR FEEDBACK SHIFT REGISTER; POLYNOMIAL GENERATOR;

ERROR DETECTION;

EID: 0142103276     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.2003.1234528     Document Type: Article

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