Optimization and fabrication of planar edge termination techniques for a high breakdown voltage and low leakage current P-i-N diode

Conference Proceedings - IEEE Applied Power Electronics Conference and Exposition - APEC

Volumn 1, Issue , 2004, Pages 241-245

  Chao, D S ^a   Hung, C C ^a   Shu, D Y ^a   Kao, M J ^a   Hsieh, W Y ^a   Tsai, M J ^a   Wang, Benson ^b   Teng, Bill ^b   Tsai, H P ^b   Lin, Rick ^b   Chen, Max ^b  

^a INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE   (Taiwan)

^b Vishay   (United States)

Author keywords

Breakdown voltage; Edge termination; Junction termination extension; Offset field plates and field limiting rings; P i n diode

Indexed keywords

COMPUTER SIMULATION; CURRENT DENSITY; DIODES; DOPING (ADDITIVES); ELECTRIC FIELD EFFECTS; LEAKAGE CURRENTS; OPTIMIZATION; SEMICONDUCTOR JUNCTIONS;

EDGE TERMINATION; JUNCTION TERMINATION EXTENSION; OFFSET FIELD PLATES AND FIELD-LIMITING RINGS; P-I-N DIODES;

ELECTRIC BREAKDOWN;

EID: 2342577414     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/APEC.2004.1295816     Document Type: Conference Paper

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