Design and optimisation of suitable edge terminations for 6.5 kV IGBTs

Microelectronics Journal

Volumn 33, Issue 9, 2002, Pages 765-769

  Vellvehi, M ^a   Flores, D ^a   Jorda X ^a   Hidalgo, S ^a   Rebollo, J ^a   Coulbeck, L ^b   Waind, P ^b   Newcombe, D ^b  

^a INSTITUTO DE MICROELECTRÓNICA DE BARCELONA   (Spain)

^b DYNEX SEMICONDUCTOR LTD   (United Kingdom)

Author keywords

Floating guard rings; High voltage IGBT; Junction termination extension

Indexed keywords

COMPUTER SIMULATION; CORRELATION METHODS; DIFFUSION; OPTIMIZATION; SEMICONDUCTOR DIODES; SEMICONDUCTOR JUNCTIONS;

FLOATING GAURD RINGS;

INSULATED GATE BIPOLAR TRANSISTORS;

EID: 0036722877     PISSN: 00262692     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0026-2692(02)00040-X     Document Type: Conference Paper

References (6)

1. Increased avalanche breakdown voltage and controlled surface electric fields using a junction termination extension (JTE) technique
2. Edge terminations for very high voltage IGBT devices
3. Theory and breakdown voltage for planar devices with a single field limiting ring
4. An analytical model for punch-through limited breakdown voltage of planar junction with multiple floating filed limiting rings
5. Analytical model of three-dimensional effect on voltage and edge peak field distributions and optimal space for planar junction with a single field limiting ring