Effects of the timing of AC stress on device degradation produced by trap states in low-temperature polycrystalline-silicon TFTs

IEEE Transactions on Electron Devices

Volumn 52, Issue 8, 2005, Pages 1766-1771

  Toyota, Yoshiaki ^a   Shiba, Takeo ^a   Ohkura, Makoto ^a  

^a HITACHI LTD   (Japan)

Author keywords

AC stress; Density of trap states; Emission time; Low temperature polycrystalline silicon thin film transistors (LTPSTFTs); Polysilicon; Trapping time

Indexed keywords

DEGRADATION; ELECTRON EMISSION; ELECTRON TRAPS; ELECTRONIC DENSITY OF STATES; ENERGY GAP; POLYSILICON;

AC STRESS; DENSITY OF TRAP STATES; EMISSION TIME; LOW TEMPERATURE POLYCRYSTALLINE SILICON THIN FILM TRANSISTORS; TRAPPING TIME;

THIN FILM TRANSISTORS;

EID: 23344435133     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2005.852726     Document Type: Article

References (14)

1. Y. Uraoka, T. Hatayama, T. Fuyuki, T. Kawamura, and Y. Tsuchihashi, "Analysis of hot-carrier effects in low temperature Poly-Si TFTs using device simulator," in Proc. IEEE Int. Conf. Microelectronic Test Structures, Mar. 2001, pp. 251-256.
2. S. Inoue and T. Shimoda, "Investigation of the relationship between hot-carrier degradation and kink effect in low-temperature polySi TFTs," in Proc. SID, 1999, pp. 452-5.
3. I. W. Wu, W. B. Jackson, T. Y. Huang, A. G. Lewis, and A. Chiang, "Mechanism of device degradation in n- and p-channel polysilicon TFTs by electrical stressing," IEEE Electron Device Lett., vol. 11, no. 4, pp. 167-169, Apr. 1990.
4. F. V. Farmakis, J. Brini, G. Kamarinos, and C. A. Dimitriadis, "Anomalous turn-on voltage degradation during hot-carrier stress in polycrystalline silicon thin-film transistors," IEEE Electron Device Lett., vol. 22, no. 2, pp. 74-6, Feb. 2001.
5. F. V. Farmakis, C. A. Dimitriadis, J. Brini, G. Kamarinos, V. K. Gueorguiev, and T. E. Ivanov, "Interface state generation during electrical stress in n-channel undoped hydrogenated polysilicon thin-film transistors," Electron. Lett., vol. 34, pp. 2356-2357, 1998.
6. K. M. Chang, Y. H. Chung, G. M. Lin, C. G. Deng, and J. H. Lin, "Enhanced degradation in polycrystalline silicon thin-film transistors under dynamic hot-carrier stress," IEEE Electron Device Lett., vol. 22, no. 10, pp. 475-477, Oct. 2001.
7. K. M. Chang, Y. H. Chung, and G. M. Lin, "Hot carrier induced degradation in the low temperature processed polycrystalline silicon thin film transistors using the dynamic stress," Jpn. J. Appl. Phys., vol. 41, pp. 1941-6, 2002.
8. Y. Uraoka, N. Hirai, H. Yano, T. Hatayama, and T. Fuyuki, "Hot carrier analysis in low-temperature polySi TFTs using picosecond emission microscope," IEEE Trans. Electron Devices, vol. 51, no. 1, pp. 28-35, Jan. 2004.
9. Y. Toyota, T. Shiba, and M. Ohkura, "A new model for device degradation in low-temperature N-channel polycrystalline silicon TFTs under ac stress," IEEE Trans. Electron Devices, vol. 51, no. 6, pp. 927-933, Jun. 2004.
10. J. G. Simmons and G. W. Taylor, "Nonequilibrium steady-state statistics and associated effects for insulators and semiconductors containing an arbitrary distribution of traps," Phys. Rev., vol. 4, pp. 502-511, Jul. 1971.
11. P. Migliorato, S. W. B. Tam, O. K. B. Lui, T. M. Brown, and M. J. Quinn, "Device physics and modeling of polySi TFTs," in Proc. SID, 1997, pp. 171-175.
12. M. Hack, A. G. Lewis, and I. W. Wu, "Physical models for degradation effects in polysilicon thin-film transistors," IEEE Trans. Electron Devices, vol. 40, no. 5, pp. 890-897, May 1993.
13. M. Hack and J. G. Shaw, "Numerical simulations of amorphous and polycrystalline silicon thin-film transistors," in Proc. Int. Conf. Solid State Device Materials, 1990, pp. 999-1002.
14. M. Matsumura, T. Kaito, M. Tai, T. Noda, T. Kamo, T. Itoga, and M. Hatano, "Analysis of transfer characteristics and trap densities of SELAX-TFT," in Proc. AM-LCD, 2004, pp. 177-178.