Design and component test of SFQ shift register memories

IEEE Transactions on Applied Superconductivity

Volumn 13, Issue 2 I, 2003, Pages 555-558

  Fujiwara, K ^a   Hoshina, H ^a   Yamashiro, Y ^a   Yoshikawa, N ^a  

^a YOKOHAMA NATIONAL UNIVERSITY   (Japan)

Author keywords

Decoder; Memory; RSFQ; Serial data; Shift register

Indexed keywords

DECODING; DELAY CIRCUITS; DIGITAL STORAGE; JOSEPHSON JUNCTION DEVICES; LOGIC CIRCUITS; LOGIC DESIGN; MICROPROCESSOR CHIPS; PACKET NETWORKS; QUANTUM ELECTRONICS; TIMING CIRCUITS;

PROPAGATION DELAY ANALYSIS;

SHIFT REGISTERS;

EID: 0042977418     PISSN: 10518223     EISSN: None     Source Type: Journal    
DOI: 10.1109/TASC.2003.813945     Document Type: Conference Paper

References (9)

1. K. K. Likharev and V. K. Semenov, "RSFQ logic/memory family: A new Josephson-junction technology for sub-terahertz-clock frequency digital systems," IEEE Trans. Appl. Superconductivity, vol. 1, pp. 1-28, March 1991.
2. S. V. Polonsky, A. F. Kirichenko, V. K. Semenov, and K. K. Likharev, "Rapid single flux quantum random access memory," IEEE Trans. Appl. Superconductivity, vol. 5, no. 2, pp. 3000-3005, June 1995.
3. S. Nagasawa, Y. Hashimoto, H. Numata, and S. Tahara, "A 380ps, 9. 5mV Josephson 4-Kbit RAM operated at a high bit yield," IEEE Trans. Appl. Superconductivity, vol. 5, no. 2, pp. 2447-2452, June 1995.
4. A. F. Kirichenko, S. Sarwana, D. K. Brock, and M. Radpavar, "Pipelined DC-powered SFQ RAM," IEEE Trans. Appl. Superconductivity, vol. 11, no. 1, pp. 537-540, Mar. 2001.
5. P. Yuh and O. A. Mukhanov, "Design and testing of rapid single flux quantum shift registers with magnetically coupled readout gates," IEEE Trans. on Applied Superconductivity, vol. 2, no. 4, pp. 214-221, Dec. 1992.
6. A. Fujimaki, Y. Takai, and N. Yoshikawa, "High-end server based on complexity-reduced architecture for superconductor technology," IEICE Transactions on Electronics, vol. E85-C, no. 3, pp. 612-616, 2002.
7. Z. J. Deng, N. Yoshikawa, S. R. Whiteley, and T. Van Duzer, "Data-driven self-timed RSFQ digital integrated circuit and system," IEEE Trans. on Applied Superconductivity, vol. 7, pp. 3634-3637, June 1997.
8. K. Fujiwara, H. Hoshina, J. Koshiyama, and N. Yoshikawa, "Design and component test of RSFQ packet decoders for shift register memories," Physica C, vol. 378-371, pp. 1475-1480, 2002.
9. S. Yorozu, Y. Kameda, H. Terai, A. Fujimaki, T. Yamada, and S. Tahara, "A single flux quantum standard logic cell library," Physica C, vol. 378-381, pp. 1471-1474, 2002.