Fabrication process of planarized multi-layer Nb integrated circuits

IEEE Transactions on Applied Superconductivity

Volumn 15, Issue 2 PART I, 2005, Pages 78-81

  Satoh, Tetsuro ^a   Hinode, Kenji ^a   Akaike, Hiroyuki ^b   Nagasawa, Shuichi ^a   Kitagawa, Yoshihiro ^a   Hidaka, Mutsuo ^a  

^a SUPERCONDUCTIVITY RESEARCH LABORATORY   (Japan)

^b NAGOYA UNIVERSITY   (Japan)

Author keywords

Integrated circuit fabrication; Niobium; Planarization; Superconducting integrated circuits

Indexed keywords

CURRENT DENSITY; ELECTRIC CURRENTS; ELECTRIC POWER SYSTEMS; FABRICATION; LITHOGRAPHY; MAGNETIC FIELD EFFECTS; MULTILAYERS; NIOBIUM; REACTIVE ION ETCHING; SUPERCONDUCTING DEVICES;

INTEGRATED CIRCUIT FABRICATION; PLANARIZATION; SINGLE-FLUX-QUANTUM (SFQ) INTEGRATED CIRCUITS; SUPERCONDUCTING INTEGERATED CIRCUITS;

INTEGRATED CIRCUITS;

EID: 22044435409     PISSN: 10518223     EISSN: None     Source Type: Journal    
DOI: 10.1109/TASC.2005.849698     Document Type: Conference Paper

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