Planarized multi-layer fabrication technology for LTS large-scale SFQ circuits

Superconductor Science and Technology

Volumn 16, Issue 12, 2003, Pages 1483-1486

  Nagasawa, Shuichi ^a   Hinode, Kenji ^a   Sugita, Masao ^a   Satoh, Tetsuro ^a   Akaike, Hiroyuki ^a   Kitagawa, Yoshihiro ^a   Hidaka, Mutsuo ^a  

^a SUPERCONDUCTIVITY RESEARCH LABORATORY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ALUMINA; CRITICAL CURRENT DENSITY (SUPERCONDUCTIVITY); ELECTRIC INSULATORS; MULTILAYERS; NIOBIUM; REACTIVE ION ETCHING; SCANNING ELECTRON MICROSCOPY; SILICA; SPUTTERING; TUNNEL JUNCTIONS;

MECHANICAL POLISHING PLANARIZATION; PLANARIZATION TECHNOLOGY; SINGLE FLUX QUANTUM CIRCUIT;

LOGIC CIRCUITS;

EID: 0347603844     PISSN: 09532048     EISSN: None     Source Type: Journal    
DOI: 10.1088/0953-2048/16/12/036     Document Type: Conference Paper

References (8)

1. Nagasawa S, Hashimoto Y, Numata H and Tahara S 1995 A 380 ps, 9.5 mW Josephson 4-Kbit RAM operated at a high bit yield IEEE Trans. Appl. Supercond. 5 2447-52
2. Nagasawa S, Tsuge H and Wada Y 1988 Planarization technology for Josephson integrated circuits IEEE Electron. Device Lett. 9 414-16
3. x-Nb Josephson process for 125 mm wafers developed in partnership with Si technology Appl. Phys. Lett. 59 2609-11
4. Numata H, Nagasawa S, Tanaka M and Tahara S 1999 Fabrication technology for high-density Josephson integrated circuits using mechanical polishing planarization IEEE Trans. Appl. Supercond. 9 3198-201
5. Numata H and Tahara S 2001 Fabrication technology for Nb integrated circuits IEICE Trans. Electron. 84 2-8
6. Numata H, Nagasawa S and Tahara S 1996 Fabrication technology for high-density Josephson LSI using an electron cyclotron resonance etching technique and a bias-sputtering planarization Supercond. Sci. Technol. 9 A42-A45
7. Zinoviev D Y, Bunyk P and Konig P M 2001 Passive interconnects: a revolutionary approach to RSFQ system design 2001 Extended Abstracts of ISEC'01 pp 175-6
8. Hinode K, Nagasawa S, Sugita M, Satoh T, Akaike H, Kitagawa Y and Hidaka M 2003 Pattern-size-free planarization for multilayered large-scale SFQ circuits IEICE Trans. Electron. E86-C accepted