Pattern-Size-Free Planarization for Multilayered Large-Scale SFQ Circuits

IEICE Transactions on Electronics

Volumn E86-C, Issue 12, 2003, Pages 2511-2513

  Hinode, Kenji ^a   Nagasawa, Shuichi ^a   Sugita, Masao ^a   Satoh, Tetsuro ^a   Akaike, Hiroyuki ^a   Kitagawa, Yoshihiro ^a   Hidaka, Mutsuo ^a  

^a SUPERCONDUCTIVITY RESEARCH LABORATORY   (Japan)

Author keywords

Multilevel wiring; Nb SFQ; Planarization; Reversal mask

Indexed keywords

CHEMICAL MECHANICAL POLISHING; CRITICAL CURRENT DENSITY (SUPERCONDUCTIVITY); ELECTRIC INSULATORS; LEAKAGE CURRENTS; PATTERN RECOGNITION; REACTIVE ION ETCHING; SCANNING ELECTRON MICROSCOPY; SILICA; SUPERCONDUCTIVITY; VISCOSITY;

MULTILEVEL WIRING; NB SFQ; PLANARIZATION; REVERSAL MASK;

LOGIC CIRCUITS;

EID: 0347272559     PISSN: 09168524     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (4)

1. S. Nagasawa, Y. Hashimoto, H. Numata, and S. Tahara, "A 380 ps, 9.5 mW Joaephson 4-Kbit RAM operated at a high bit yield," IEEE Trans. Appl. Supercond., vol.5, no.2, pp.2447-2452, June 1995.
2. H. Numata and S. Tahara, "Fabrication technology for Nb integrated circuits," IEICE Trans. Electron., vol.E84-C, no.1, pp.2-8, Jan. 2001.
3. T. Doi, ed., Details of Semiconductor CMP Technology, pp.121, 128, 163, 169, etc., Kogyochosakai, Tokyo, 2001.
4. M. Kodera, A. Shigeta, G. Toyota, and R. Nakata, The Japan Society for Abrasive Technology Annual Meeting Proceedings, p.291, 1995.