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1
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An experiment in the design and development of a multimedia processor for mobile computing
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(DSP2002-130-137), Oct.
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M. Fukase, K. Shioji, N. Imai, D. Murakami, and K. Mikuni, "An Experiment in the Design and Development of a Multimedia Processor for Mobile Computing," Technical Report of IEICE, Vol. 102, No. 400 (DSP2002-130-137), pp13-18, Oct. 2002.
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Fukase, M.1
Shioji, K.2
Imai, N.3
Murakami, D.4
Mikuni, K.5
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2
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0035690014
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Prototyping a java-embedded multimedia processor
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Nov.
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M. Fukase, P. Khondkar, and T. Nakamura, "Prototyping a Java-Embedded Multimedia Processor," Proc. of IECON'01, pp. 2126-2130, Nov. 2001.
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Proc. of IECON'01
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Fukase, M.1
Khondkar, P.2
Nakamura, T.3
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3
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21844445015
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Enhancing execution bandwidth of java-embedded processor
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Mar.
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P. Khondkar, M. Fukase, and T. Nakamura, "Enhancing Execution Bandwidth of Java-Embedded Processor," Information, Vol. 7, No. 2, pp. 215-225, Mar. 2004.
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Information
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Fukase, M.2
Nakamura, T.3
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An architecture to allow intrinsic concurrency on java processors for embedded systems
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May
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P. Khondkar, M. Fukase, C. D. Lima, and T. Nakamura, "An Architecture to Allow Intrinsic Concurrency on Java Processors for Embedded Systems," ibid, Vol. 7, No. 3, pp. 351-366, May 2004.
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(2004)
Information
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Java runtime systems: Characterization and architectural implications
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Feb.
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21844468484
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Could wave pipeline overcome commodity pipelines?
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In press
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R. Egawa, M. Fukase, T. Sato, and T. Nakamura, "Could Wave Pipeline Overcome Commodity Pipelines?," Information, 2004 (In press).
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(2004)
Information
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Egawa, R.1
Fukase, M.2
Sato, T.3
Nakamura, T.4
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Designing a wave-pipelined vector processor
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Oct.
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M. Fukase, T. Sato, R. Egawa, and T. Nakamura, "Designing a Wave-Pipelined Vector Processor," Proc. of the Tenth Workshop on Synthesis and System Integration of Mixed Technologies, pp. 351-356, Oct. 2001.
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(2001)
Proc. of the Tenth Workshop on Synthesis and System Integration of Mixed Technologies
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Fukase, M.1
Sato, T.2
Egawa, R.3
Nakamura, T.4
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10
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Scaling up of wave-pipelines
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Jan.
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M. Fukase, T. Sato, R. Egawa, and T. Nakamura, "Scaling up of Wave-Pipelines," Proc. of the Fourteenth International Conference on VLSI Design, pp. 439-445, Jan. 2001.
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(2001)
Proc. of the Fourteenth International Conference on VLSI Design
, pp. 439-445
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Fukase, M.1
Sato, T.2
Egawa, R.3
Nakamura, T.4
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14
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21844456248
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Architectural aspects of multimedia mobile processor cores
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Japan, Aug.
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K. Mikuni, Y. Nakamura, and M. Fukase, "Architectural Aspects of Multimedia Mobile Processor Cores," Proc. of 2003 Tohoku-Section Joint Convention of Institutes of Electrical and Information Engineers, Japan, Aug. 2003.
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(2003)
Proc. of 2003 Tohoku-section Joint Convention of Institutes of Electrical and Information Engineers
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Mikuni, K.1
Nakamura, Y.2
Fukase, M.3
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Implementation of a multimedia mobile processor
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Sept.
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K. Mikuni, Y. Nakamura, N. Imai, M. Fukase, and T. Sato, "Implementation of a Multimedia Mobile Processor," FIT2003, Sept. 2003.
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FIT2003
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Mikuni, K.1
Nakamura, Y.2
Imai, N.3
Fukase, M.4
Sato, T.5
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17
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0036818390
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Minimizing memory access energy in embedded systems by selective instruction compression
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Oct.
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L. Benini, A. Macii, E. Macii, and M. Poncino, "Minimizing Memory Access Energy in Embedded Systems by Selective Instruction Compression," IEEE Trans. on VLSI Syst., Vol. 10, No. 5, pp. 521-531, Oct. 2002.
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Benini, L.1
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Poncino, M.4
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19
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0041562664
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Programmable stream processors
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Aug.
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U. J. Kapasi, S. Rixner, W. J. Dally, B. Khailany, J. H. Ahn, P. Mattson, J. D. Owens, "Programmable Stream Processors," Computer Magazine, Vol. 36, No. 8, pp. 54-62, Aug. 2003.
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Computer Magazine
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Kapasi, U.J.1
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Khailany, B.4
Ahn, J.H.5
Mattson, P.6
Owens, J.D.7
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20
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0036733204
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An instruction-level energy model for embedded VLIW architecture
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Sept.
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M. Sami, D. Sciuto, C. Silvano, and V. Zaccaria, "An Instruction-Level Energy Model for Embedded VLIW Architecture," IEEE Trans. on CAD and Syst., Vol. 21, No. 9, pp. 998-1010, Sept. 2002.
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IEEE Trans. on CAD and Syst.
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