Scaling of shallow trench isolation with stress control for 65nm node and beyond

International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT

Volumn 1, Issue , 2004, Pages 548-553

  Kuroi, Takashi ^a   Horita, Katsuyuki ^a  

^a RENESAS TECHNOLOGY CORP   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ASPECT RATIO; CHEMICAL VAPOR DEPOSITION; MICROPROCESSOR CHIPS; MOSFET DEVICES; STRAIN RATE; STRESS ANALYSIS; TECHNOLOGY TRANSFER; TENSILE STRESS; ULSI CIRCUITS;

PROCESS TECHNOLOGIES; SHALLOW TRENCH ISOLATION (STI); STRESS CONTROL; STRESS REDUCTION;

TRENCHING;

EID: 21644481154     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (20)

1. P. C. Faza et. al., IEDM Tech. Dig. p.57 1993
2. A. Bryant et. al., IEDM Tech. Dig. p.671 1994
3. M. Nandakumar et. al., IEDM Tech Dig. p. 133 1998
4. International Technology Roadmap for semi-conductors 2003 editions, Semiconductor Industry Association.
5. E. A. Fitzgerald et. al., J. Vac. Sci. Tech. Vol.B 10 p. 1807 1992
6. N. Ohki et. al., IEDM Tech. Dig. p.433 2001
7. T. Gahni et. al., IEDM Tech. Dig. p. 978 2003
8. G. Scott et. al., IEDM Tech. Dig. p.978 1999
9. P. Smeys et. al., IEEE Trans. Electron Devices vol.46, p.1245 1999
10. T. Kuroi et. al, IEDM Tech. Dig. p.141 1998
11. N. Shigyo et. al., IEEE Trans. Electron Devices vol.35, p.945 1988
12. K. Horita et.al., Symp. on VLSI Tech. Dig. P. 178 2000
13. J. W. Heo et.al., Symp. on VLSI Tech. Dig. P. 151 2003
14. J. W. Heo et.al., Symp. on VLSI Tech. Dig. P. 102 2002
15. N. Endo et.al., IEEE Trans. Electron Devices vol.33, p. 1659 1986
16. Y. W. Cha et.al., Symp. on VLSI Tech. Dig. P. 153 2003
17. M. Ishibashi et. al., to be presented at SSDM 2004
18. J. Damiano et.al., Symp. on VLSI Tech. Dig. P.202 1998
19. T. Uchida et.al., Jpn. J. Appl. Phys. vol.35, p.4265 1996
20. J. J. Burkhardt et. Al., J. Electrochemical Society, 147(9) p. 3482(2000)