Wrong path events: Exploiting unusual and illegal program behavior for early misprediction detection and recovery

Proceedings of the Annual International Symposium on Microarchitecture, MICRO

Volumn , Issue , 2004, Pages 119-128

  Armstrong, David N ^a   Kim, Hyesoon ^a   Mutlu, Onur ^a   Patt, Yale N ^a  

^a The University of Texas at Austin   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BRANCH PREDICTION; DATA SPECULATION; MISPREDICTION DETECTION; WRONG PATH EVENTS;

BENCHMARKING; DATA REDUCTION; ENERGY UTILIZATION; INFORMATION ANALYSIS; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS;

DATA PROCESSING;

EID: 21644466472     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (20)

1. J. L. Aragon, J. Gonzalez, A. Gonzalez, and J. E. Smith. Dual path instruction processing. In Proceedings of the 2002 International Conference on Supercomputing, 2002.
2. D. N. Armstrong, H. Kim, O. Mutlu, and Y. N. Patt. Wrong path events: Exploiting unusual and illegal program behavior for early misprediction detection and recovery. Technical Report TR-HPS-2004-002, HPS Technical Report, 2004.
3. M. Bekerman, A. Yoaz, F. Gabbay, S. Jourdan, M. Kalaev, and R. Ronen. Early load address resolution via register tracking. In Proceedings of the 27th Annual International Symposium on Computer Architecture, pages 306-315, 2000.
4. J. O. Bondi, A. K. Nanda, and S. Dutta. Integrating a misprediction recovery cache (MRC) into a superscalar pipeline. In Proceedings of the 29th Annual ACM/IEEE International Symposium on Microarchitecture, pages 14-23, Dec. 1996.
5. M. G. Butler. Aggressive Execution Engines for Surpassing Single Basic Block Execution. PhD thesis, University of Michigan, 1993.
6. M. Evers and T.-Y. Yeh. Understanding branches and designing branch predictors for high-performance microprocessors. Proceedings of the IEEE, 89(11):1610-1620, Nov. 2001.
7. A. Falcón, J. Stark, A. Ramirez, K. Lai, and M. Valero. Prophet-critic hybrid branch prediction. In Proceedings of the 31st Annual International Symposium on Computer Architecture, 2004.
8. A. Glew. Branch and computation refi nement. Unpublished Manuscript, University of Wisconsin, Jan. 2000.
9. E. Jacobsen, E. Rotenberg, and J. E. Smith. Assigning confidence to conditional branch predictions. In Proceedings of the 29th Annual ACM/IEEE International Symposium on Microarchitecture, pages 142-152, 1996.
10. D. A. Jiménez, S. W. Keckler, and C. Lin. The impact of delay on the design of branch predictors. In Proceedings of the 33rd Annual ACM/IEEE International Symposium on Microarchitecture, pages 67-76, 2000.
11. S. Jourdan, T.-H. Hsing, J. Stark, and Y. N. Patt. The effects of mispredicted-path execution on branch prediction structures. In Proceedings of the 1996 ACM/IEEE Conference on Parallel Architectures and Compilation Techniques, pages 58-67, 1996.
12. R. E. Kessler. The Alpha 21264 microprocessor. IEEE Micro, 19(2):24-36, 1999.
13. S. Manne, A. Klauser, and D. Grunwald. Pipeline gating: Speculation control for energy reduction. In Proceedings of the 25th Annual International Symposium on Computer Architecture, pages 132-141, 1998.
14. S. McFarling. Combining branch predictors. Technical Report TN-36, Digital Western Research Laboratory, June 1993.
15. A. Moshovos, S. E. Breach, T. N. Vijaykumar, and G. S. Sohi. Dynamic speculation and synchronization of data dependences. In Proceedings of the 24th Annual International Symposium on Computer Architecture, 1997.
16. O. Mutlu, H. Kim, D. N. Armstrong, and Y. N. Patt. Understanding the effects of wrong-path memory references on processor performance. In Third Workshop on Memory Performance Issues, 2004.
17. J. Pierce and T. Mudge. The effect of speculative execution on cache performance. In Proceedings of the International Parallel Processing Symposium, pages 172-179, 1994.
18. G. S. Sohi, S. Breach, and T. N. Vijaykumar. Multiscalar processors. In Proceedings of the 22nd Annual International Symposium on Computer Architecture, pages 414-425, 1995.
19. T.-Y. Yeh and Y. N. Patt. Alternative implementations of two-level adaptive branch prediction. In Proceedings of the 19th Annual International Symposium on Computer Architecture, pages 124-134, 1992.
20. A. Yoaz, M. Erez, R. Ronen, and S. Jourdan. Speculation techniques for improving load related instruction scheduling. In Proceedings of the 26th Annual International Symposium on Computer Architecture, pages 42-53, 1999.