IP integration methodology for SoC design

Proceedings of the International Conference on Microelectronics, ICM

Volumn , Issue , 2004, Pages 343-346

  Abbes, F ^a,b   Casseau, E ^b   Abid, M ^a   Coussy, P ^b   Legoff, J B ^b  

^a UNIVERSITY OF SFAX   (Tunisia)

^b UNIVERSITÉ DE BRETAGNE SUD   (France)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED SOFTWARE ENGINEERING; CONSTRAINT THEORY; INTERFACES (COMPUTER); MATHEMATICAL MODELS; OPTIMIZATION; PARAMETER ESTIMATION; SYSTEMS ANALYSIS;

DESIGN CYCLE; REGISTER TRANSFER; SYSTEM ON CHIP (SOC); VIRTUAL COMPONENTS;

INTELLECTUAL PROPERTY;

EID: 21644463996     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)

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2. G. Cyr, G. Bois, M. Aboulhamid « Generation of processor interface for SoC using VSIA recommendations », submitted to IEE Proc. - Computers and Digital Techniques, 11/2002.
3. http://soclib.lip6.fr/
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7. R.Damaševičius, V.Štuikys. «Wrapping of Soft IPs for Interface-based Design Using Heterogeneous Metaprogramming», informatica, 2003, Vol. 14, No. 1, pp. 3-18. ISSN 0868-4952
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9. Sonics Inc, "Open Core Protocol Specification 1.0", 2000
10. Virtual Component Interface Standard VSI Alliance™, OCB 2 2.0, On-Chip Bus Development Working Group April 2001
11. Y. Cho, G Lee, Sungjoo Yoo, K. Choi, and N.Zergainoh, « Scheduling and Timing Analysis of HW/SW On-Chip Communication in MP SoC Design » (DATE'03 Designers' Forum), Munich, Germany (2003)