Scheduling and timing analysis of HW/SW on-chip communication in MP SoC design

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2003, Pages 132-137

  Cho, Youngchul ^a   Lee, Ganghee ^a   Yoo, Sungjoo ^b   Choi, Kiyoung ^a   Zergainoh, Nacer Eddine ^b  

^a Seoul National University   (South Korea)

^b TIMA LABORATORY   (France)

Author keywords

[No Author keywords available]

Indexed keywords

COMMUNICATION INTERFACE; CONTEXT SWITCHING; DESIGNING SOFTWARES; INTEGER LINEAR PROGRAMMING; INTERRUPT SERVICE ROUTINE; ON CHIP COMMUNICATION; ON-CHIP COMMUNICATION NETWORKS; PHYSICAL COMMUNICATIONS;

COMMUNICATION; DESIGN; EXHIBITIONS; HEURISTIC ALGORITHMS; INTEGER PROGRAMMING; SCHEDULING;

MICROPROCESSOR CHIPS;

EID: 84893766957     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2003.1186684     Document Type: Conference Paper

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