A design methodology for IP integration

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 4, Issue , 2002, Pages

  Coussy, Philippe ^a   Baganne, Adel ^a   Martin, Eric ^a  

^a UNIVERSITÉ DE BRETAGNE SUD   (France)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; DIGITAL SIGNAL PROCESSING; INTEGRATED CIRCUIT LAYOUT; INTELLECTUAL PROPERTY; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS;

INTELLECTUAL PROPERTY EXECUTION REQUIREMENTS MODEL; SYSTEM-ON-A-CHIP;

ELECTRIC NETWORK SYNTHESIS;

EID: 0036290718     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (13)

1. VSI abandons plans for system-chip bus
2. Interface-based design
3. Techniques for reducing read latency of core bus wrapper
4. CoWare a design environment for heterogeneous hw/sw systems
5. Automatic synthesis of interfaces between incompatible protocols
6. Synthesis of communication interfaces for SOC using VSIA recommendation
7. A formal technique for hardware interface design