Lightweight implementation of the POSIX threads API for an on-chip MIPS multiprocessor with VCI interconnect

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2003, Pages 51-56

  Petrot, Frédéric ^a   Gomez, Pascal ^a  

^a UNIVERSITÉ PIERRE ET MARIE CURIE   (France)

Author keywords

[No Author keywords available]

Indexed keywords

ARCHITECTURAL PARAMETERS; COMPLIANT INTERCONNECTS; MULTITHREADED; ON CHIPS; ON-CHIP MULTIPROCESSOR; POSIX THREADS; TARGET ARCHITECTURES; VIDEO DECODERS;

EXHIBITIONS;

MULTIPROCESSING SYSTEMS;

EID: 37149008575     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2003.1253805     Document Type: Conference Paper

References (10)

1. VSI Alliance. Virtual Component Interface Standard (OCB 2 2.0), August 2000
2. T. R. Halfhill. Embedded market breaks new ground. Microprocessor Report, January 2000
3. J. Archibald and J.-L. Baer. Cache coherence protocols: Evaluation using a multiprocessor simulation model. ACM Transactions on Computer Systems, 4(4):273-298, 1986
4. T. P. Baker, F. Mueller, and V. Rustagi. Experience with a prototype of the POSIX ?minimal realtime system profile. In Proceedings 11th IEEE Workshop on Real-Time Operating Systems and Software. RTOSS ?94, pages 12-16, Seattle, WA, USA, 1994
5. OSEK/VDX. OSEK/VDX Operating System Specification 2.2, September 2001. http://www.osek-vdx.org.
6. A. S. Tanenbaum. Distributed Operating Systems, chapter 6.3, pages 315-333. Prentice Hall, 1995
7. M. Kandemir and A. Choudhary. Compiler-directed scratch pad memory hierarchy design and management. In Design Automation Conference, pages 628-633, New Orleans, LA, June 2002
8. J. Montanaro et al. A 160mhz 32b 0.5w cmos risc microprocessor. In ISSCC Digest of Technical Papers, pages 214- 215, February 1996
9. Frédéric Pétrot, Denis Hommais, and Alain Greiner. Cycle precise core based hardware/software system simulation with predictable event propagation. In Proceeding of the 23rd Euromicro Conference, pages 182-187, Budapest, Hungary, September 1997. IEEE.
10. Jr. R. H. Halstead and T. Fujita. MASA: A multithreaded processor architecture for parallel symbolic computing. In 15th Annual International Symposium on Computer Architecture, pages 443-451, June 1988