Optimal superblock scheduling using enumeration

Proceedings of the Annual International Symposium on Microarchitecture, MICRO

Volumn , Issue , 2004, Pages 283-293

  Shobaki, Ghassan ^a   Wilken, Kent ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Compiler optimizations; Enumeration; Global instruction scheduling; Optimal scheduling; Superblock

Indexed keywords

COMPILER OPTIMIZATIONS; ENUMERATION; GLOBAL INSTRUCTION SCHEDULING; OPTIMAL SCHEDULING; SUPERBLOCK;

COMPUTATIONAL COMPLEXITY; CONSTRAINT THEORY; DYNAMIC PROGRAMMING; FUNCTIONS; HEURISTIC METHODS; OPTIMIZATION; PROBLEM SOLVING; SCHEDULING; STORAGE ALLOCATION (COMPUTER);

COMPUTER PROGRAMMING;

EID: 21644448807     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (19)

1. D. Bernstein and M. Rodeh, "Global Scheduling for Superscalar Machines". In Proc. of Programming Language Design and Implementation, Jun. 1991, pp 241-255.
2. J. Bharadwaj and C. McKinsey, "Wavefront Scheduling: Path Based Data Representation and Scheduling of Subgraphs". Journal of Instruction-Level Parallelism, v. 1 n. 6, pp. 1-6, 2000.
3. C. Chekuri , R. Johnson, R. Motwani , B. Natarajan, B. Rau and M. Schlansker. "Profile-Driven Instruction Level Parallel Scheduling with Applications to Superblocks". In Proc. 29th Int. Symp. on Microarchitecture, Dec. 1996, pp. 58-67.
4. T. Cormen, C. Leiserson and R. Rivest. 1990. Introduction to Algorithms. MIT Press.
5. H. Chou and C. Chung. "An Optimal Instruction Scheduler for Superscalar Processor". IEEE Trans. on Parallel and Distributed Systems, v.6 n.3, pp. 303-313, Mar. 1995.
6. B. Deitrich and W. Hwu. "Speculative Hedge: Regulating Compile-Time Speculation Against Profile Variations". In Proc. 29th Int. Symp. on Microarchitecture, Dec. 1996, pp. 70-79.
7. A. Eichenberger and W. Meleis, "Balance Scheduling: Weighting Branch Tradeoffs in Superblocks". In Proc. 32nd Int. Symp. on Microarchitecture, Nov. 1999, pp. 272-283.
8. P. Faraboschi, J. Fisher and C. Young. "Instruction Scheduling for Instruction Level Parallel Processors". Proceedings of the IEEE, v. 89 n. 11, pp. 1638-1659, Nov. 2001.
9. J. Fisher. "Trace Scheduling: A Technique for Global Micro-Code Compaction". IEEE Trans. on Computers, v. 30 n.7, pp. 478-490, Jul. 1981.
10. R. Hank, S. Mahlke, R. Bringmann, J. Gyllenhaal and W. Hwu. "Superblock Formation Using Static Program Analysis". In Proc. 26th Int. Symp. on Microarchitecture, Dec. 1993, pp. 247-255.
11. J. Hennessy and T. Gross. "Postpass Code Optimization of Pipeline Constraints". ACM Trans. on Programming Languages and Systems, v. 5, pp. 422-448, 1983.
12. W. Hwu, S. Mahlke, W. Chen, P. Chang, N. Warter, R. Bringmann, R. Ouellette, R. Hank, T. Kiyohara, G. Haab, J. Holm and D. Lavery, "The Superblock: An Effective Technique for VLIW and Superscalar Compilation". Journal of Supercomputing, v. 7 n. 1/2, pp. 229-248, 1993.
13. M. Langevin and E. Cerny. "A Recursive Technique for Computing Lower-Bound Performance of Schedules". ACM Trans. on Design Automation of Electronic Systems, v. 1 n. 4, pp. 443-456, Oct. 1996.
14. W. Meleis, A. Eichenberger and I. Baev. "Scheduling Superblocks with Bound-Based Branch Trade-offs". IEEE Trans. on Computers, v. 50 n. 8, pp. 784-797, Aug. 2001.
15. S. Muchnick. 1997. Advanced Compiler Design and Implementation. Morgan Kaufmann.
16. M. Narasimhan and J. Ramanujam, "A Fast Approach to Computing Exact Solutions to the Resource-Constrained Scheduling Problem". ACM Trans. on Design Automation of Electronic Systems, v.6 n.4, p.490-500, Oct. 2001.
17. M. Rim and R. Jain. "Lower-Bound Performance Estimation for the High-Level Synthesis Scheduling Problem". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, v.13 n. 4, pp. 451-458, Apr. 1994.
18. L. Wolsey. 1998. Integer Programming. John Wiley and Sons.
19. K. Wilken, G. Shobaki, J. Liu and M. Heffernan, "A Faster Approach to Optimal Resource-Constrained Scheduling". Submitted for publication.