Scheduling superblocks with bound-based branch trade-offs

IEEE Transactions on Computers

Volumn 50, Issue 8, 2001, Pages 784-797

  Meleis, Waleed M ^a   Eichenberger, Alexandre E ^a,c   Baev, Ivan D ^a,b  

^a IEEE   (United States)

^b Northeastern University   (United States)

^c North Carolina State University   (United States)

Author keywords

ILP compiler technique; Lower bound; Scheduling heuristic; Superblock

Indexed keywords

BOUND BASED BRANCH TRADE OFFS; INSTRUCTION LEVEL PARALLELISM; SCHEDULING HEURISTIC; SCHEDULING SUPERBLOCKS;

ALGORITHMS; COMPUTATIONAL COMPLEXITY; DATA STRUCTURES; HEURISTIC PROGRAMMING; PIPELINE PROCESSING SYSTEMS; PROGRAM COMPILERS; RESPONSE TIME (COMPUTER SYSTEMS); VERY LONG INSTRUCTION WORD ARCHITECTURE;

PARALLEL PROCESSING SYSTEMS;

EID: 0035415677     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.946999     Document Type: Article

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