-
1
-
-
33746994370
-
Lower-bounds on the iteration and initiation interval of functional pipelining and loop folding
-
(to appear).
-
BENNOUR, I. AND ABOULHAMID, E. M. 1997. Lower-bounds on the iteration and initiation interval of functional pipelining and loop folding. Des. Autom. Embedded Syst. (to appear).
-
(1997)
Des. Autom. Embedded Syst.
-
-
Bennour, I.1
Aboulhamid, E.M.2
-
3
-
-
0022276833
-
Parallel and pipelined VLSI implementation of signal processing algorithms
-
S. Y. Kung, H. J. Whitehouse, T. Kailath, Eds., Prentice-Hall, Englewood Cliffs, NJ.
-
DEWILDE, P., DEPRETTERE, E., AND NOUTA, R. 1985. Parallel and pipelined VLSI implementation of signal processing algorithms. In VLSI and Modern Signal Processing, S. Y. Kung, H. J. Whitehouse, T. Kailath, Eds., Prentice-Hall, Englewood Cliffs, NJ.
-
(1985)
VLSI and Modern Signal Processing
-
-
Dewilde, P.1
Deprettere, E.2
Nouta, R.3
-
4
-
-
0003453799
-
-
Prentice Hall, Englewood Cliffs, NJ.
-
GAJSKI, D. D., VAHID, F., NARAYAN, S., AND GONG, J. 1994. Specification and Design of Embedded Systems. Prentice Hall, Englewood Cliffs, NJ.
-
(1994)
Specification and Design of Embedded Systems
-
-
Gajski, D.D.1
Vahid, F.2
Narayan, S.3
Gong, J.4
-
6
-
-
0026174907
-
Simultaneous scheduling and allocation for cost constrained optimal architectural synthesis
-
(San Francisco, CA, June 17-21)
-
GEBOTYS, C. H. AND ELMASRY, M. I. 1991. Simultaneous scheduling and allocation for cost constrained optimal architectural synthesis. In Proceedings of DAC (San Francisco, CA, June 17-21), 2-7.
-
(1991)
Proceedings of DAC
, pp. 2-7
-
-
Gebotys, C.H.1
Elmasry, M.I.2
-
7
-
-
0026139605
-
A formal approach to the scheduling problem in high level synthesis
-
HWANG, C.-T., LEE, J.-H., AND HSU, Y.-C. 1991. A formal approach to the scheduling problem in high level synthesis. IEEE Trans. CAD 10, 464-475.
-
(1991)
IEEE Trans. CAD
, vol.10
, pp. 464-475
-
-
Hwang, C.-T.1
Lee, J.-H.2
Hsu, Y.-C.3
-
9
-
-
0024887707
-
Experience with the ADAM synthesis system
-
(Las Vegas, NE, June 25-29)
-
JAIN, R., KUCUKCAKAR, K., MLINAR, M. J., AND PARKER, A. C. 1989. Experience with the ADAM synthesis system. In Proceedings of DAC (Las Vegas, NE, June 25-29), 56-61.
-
(1989)
Proceedings of DAC
, pp. 56-61
-
-
Jain, R.1
Kucukcakar, K.2
Mlinar, M.J.3
Parker, A.C.4
-
10
-
-
0012948391
-
Local microcode generation in system design
-
P. Marwedel and G. Goossens, Eds., Kluwer Academic, Boston, MA, Ch.
-
LANGEVIN, M., CERNY, E., WILBERG, J., AND VIERHAUS, H.-T. 1995. Local microcode generation in system design. In Code Generation for Embedded Processors, P. Marwedel and G. Goossens, Eds., Kluwer Academic, Boston, MA, Ch. 10, 171-187.
-
(1995)
Code Generation for Embedded Processors
, vol.10
, pp. 171-187
-
-
Langevin, M.1
Cerny, E.2
Wilberg, J.3
Vierhaus, H.-T.4
-
11
-
-
0024134190
-
Tutorial on high-level synthesis
-
(Anaheim, CA, June 12-15)
-
MCFARLAND, M. C., PARKER, A. C., AND CAMPOSANO, R. 1988. Tutorial on high-level synthesis. In Proceedings of DAC (Anaheim, CA, June 12-15), 330-336.
-
(1988)
Proceedings of DAC
, pp. 330-336
-
-
Mcfarland, M.C.1
Parker, A.C.2
Camposano, R.3
-
12
-
-
3042918654
-
A high-level synthesis technique based on linear programming
-
Computer Engineering and Science Dept., Case Western Reserve Univ., Nov.
-
PAPACHRISTOU, C. A. AND KONUK, H. 1989. A high-level synthesis technique based on linear programming. Tech. Rep., Computer Engineering and Science Dept., Case Western Reserve Univ., Nov.
-
(1989)
Tech. Rep.
-
-
Papachristou, C.A.1
Konuk, H.2
-
13
-
-
0023983163
-
Sehwa: A software package for synthesis of pipelines from behavioral specifications
-
PARK, N. AND PARKER, A. C. 1988. Sehwa: A software package for synthesis of pipelines from behavioral specifications. IEEE Trans. CAD 7, 356-370.
-
(1988)
IEEE Trans. CAD
, vol.7
, pp. 356-370
-
-
Park, N.1
Parker, A.C.2
-
14
-
-
0024682923
-
Force-directed scheduling for the behavioral synthesis of ASIC's
-
PAULIN, P. G. AND KNIGHT, J. P. 1989. Force-directed scheduling for the behavioral synthesis of ASIC's. IEEE Trans. CAD 8, 661-679.
-
(1989)
IEEE Trans. CAD
, vol.8
, pp. 661-679
-
-
Paulin, P.G.1
Knight, J.P.2
-
15
-
-
0028447653
-
Estimating implementation bounds for real time DSP application specific circuits
-
RABAEY, J. M. AND POTKONJAK, M. 1994. Estimating implementation bounds for real time DSP application specific circuits. IEEE Trans. CAD 13, 669-683.
-
(1994)
IEEE Trans. CAD
, vol.13
, pp. 669-683
-
-
Rabaey, J.M.1
Potkonjak, M.2
-
16
-
-
0028413050
-
Lower-bound performance estimation for high-level synthesis scheduling problem
-
RIM, M. AND JAIN, R. 1994. Lower-bound performance estimation for high-level synthesis scheduling problem. IEEE Trans. CAD 13, 451-458.
-
(1994)
IEEE Trans. CAD
, vol.13
, pp. 451-458
-
-
Rim, M.1
Jain, R.2
-
17
-
-
0027612296
-
Estimating architectural resources and performance for high-level synthesis applications
-
SHARMA, A. AND JAIN, R. 1993. Estimating architectural resources and performance for high-level synthesis applications. IEEE Trans. VLSI Syst. 1.
-
(1993)
IEEE Trans. VLSI Syst.
, vol.1
-
-
Sharma, A.1
Jain, R.2
-
18
-
-
0027797139
-
Execution interval analysis under resource constraints
-
(Santa Clara, CA, Nov. 7-11)
-
TIMMER, A. H. AND JESS, J. A. G. 1993. Execution interval analysis under resource constraints. In Proceedings of ICCAD (Santa Clara, CA, Nov. 7-11), 454-459.
-
(1993)
Proceedings of ICCAD
, pp. 454-459
-
-
Timmer, A.H.1
Jess, J.A.G.2
|