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Volumn 41, Issue 1, 2005, Pages 35-47

Reconfigurable discrete wavelet transform processor for heterogeneous reconfigurable multimedia systems

Author keywords

Discrete wavelet transform; Energy efficiency; Heterogeneous reconfigurable multimedia systems; Lifting scheme; Reconfigurable computing

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTATIONAL METHODS; DIGITAL SIGNAL PROCESSING; EMBEDDED SYSTEMS; ENERGY EFFICIENCY; GRAPHIC METHODS; INTEGRATION; WAVELET TRANSFORMS;

EID: 21544471252     PISSN: 13875485     EISSN: None     Source Type: Journal    
DOI: 10.1007/s11265-005-6249-z     Document Type: Article
Times cited : (9)

References (21)
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    • Chen, C.Y.1    Yang, Z.L.2    Wang, T.C.3    Chen, L.G.4
  • 13
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    • M. Ferretti and D. Rizzo, "A Parallel Architecture for the 2-D Discrete Wavelet Transform with Integer Lifting Scheme," The Journal of VLSI Signal Processing, vol. 28, July 2001, pp. 165-185.
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    • Ferretti, M.1    Rizzo, D.2
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    • A VLSI architecture for lifting-based forward and inverse wavelet transform
    • K. Andra, C., Chakrabarti, and T. Acharya, "A VLSI Architecture for Lifting-Based Forward and Inverse Wavelet Transform," IEEE Transactions on Signal Processing, vol. 50, no. 4, 2002, pp. 966-977.
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.