1.2 nm HfSiON/SiON stacked gate insulators for 65-nm-Node MISFETs

Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers

Volumn 44, Issue 4 B, 2005, Pages 2330-2335

  Saitoh, Motofumi ^a   Terai, Masayuki ^a   Ikarashi, Nobuyuki ^a   Watanabe, Heiji ^a,b   Fujieda, Shinji ^a   Iwamoto, Toshiyuki ^a   Ogura, Takashi ^a   Morioka, Ayuka ^a   Watanabe, Koji ^a   Tatsumi, Toru ^a   Watanabe, Hirohito ^a  

^a NEC CORPORATION   (Japan)

^b OSAKA UNIVERSITY   (Japan)

Author keywords

65 nm node; FET; Gate insulator; Hf; High k; Interfacial trap states; Leakage current; Mobility; MOS; Nitridation

Indexed keywords

65-NM-NODE; HIGH-K; INTERFACIAL TRAP STATES; MOBILITY; NITRIDATION;

DIELECTRIC MATERIALS; GATES (TRANSISTOR); HAFNIUM COMPOUNDS; INTERFACES (MATERIALS); LEAKAGE CURRENTS; PERMITTIVITY; SILICA;

MISFET DEVICES;

EID: 21244453921     PISSN: 00214922     EISSN: None     Source Type: Journal    
DOI: 10.1143/JJAP.44.2330     Document Type: Conference Paper

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